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| | Adaptec Article: PCI, 64-Bit and 66-MHz Benefits |
 | | As we said before, data and addressing are multiplexed over the same pins, either AD[31::00] for 32 bits or AD[31::00] and AD[64::32] for 64 bits. | | | Since the OS plays a huge role in system performance by addressing and transferring data to and from memory, when the OS supports only 32-bits when the hardware supports 64 bits, the system is still somewhat limited. | | | To create a 64-bit driver, you must modify the DMA descriptors to address 64 bits of memory so the hardware can access the pointers to the data in this memory range. |
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http://www.adaptec.com/worldwide/product/markeditorial.html?prodkey=pci64bit&cat=/Technology/SCSI/&type=SCSI
(2144 words)
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| | pentopt.txt |
| | The BTB entry for a control transfer instruction is identified by bits 2-31 of the address of the last byte in the instruction. | | | Each entry is identified by bits 2-31 of the address of the last byte of the control transfer instruction it belongs to. | | | Each entry is identified by bits 4-31 of the address of the last byte of the control transfer instruction it belongs to. |
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http://www.csse.monash.edu.au/~greif/cse3306/pentopt.txt
(19797 words)
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| | 3 Bit Manipulation (bits.hhf) |
| | The bits.distribute function grabs the L.O. 16 bits of source and inserts these bits at positions 0, 1, 2, 3, 16, 17, 18, 19, 20, 21, 22, 23, and 28, 29, 30, and 31 into the value $1234_5678 and returns the result in EAX. | | | If you want to compute the number of bits in an eight-bit operand it's probably faster to write a simple loop that rotates all the bits in the source operand and adds the carry into the accumulating sum. | | | This function takes the L.O. n bits of source, where n is the number of "1" bits in mask, and inserts these bits into dest at the bit positions specified by the "1" bits in mask. |
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http://webster.cs.ucr.edu/AsmTools/HLA/HLADoc/HLAstdlib/hlastdliba4.html
(19797 words)
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| | OpenVMS Calling Standard |
| | Bits <31:29> must be 0; they are reserved to Digital for future use. | | | A variant of the unaligned bit string descriptor is used to specify bit strings where the string is viewed as a one-dimensional bit array with user-specified bounds. | | | A variant of the noncontiguous array descriptor is used to specify an array of unaligned bit strings. |
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http://h71000.www7.hp.com/doc/72final/5973/5973pro_012.html
(19797 words)
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| | Writing 64-bit programs |
| | Apart from the above, the only new instruction of any note usable by programmers is MOVSXD which can move 32-bits of data from a register or from memory into a 64-bit register, sign extending bit 31 into bit 63. | | | This happens irrespective of the value of bit 31 of RAX (this is not the same as sign-extension). | | | You can still access the second byte of RAX,RBX,RCX and RDX (bits 8 to 15) by using the existing names AH,BH,CH,DH as in the 86 processor. |
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http://www.jorgon.freeserve.co.uk/GoasmHelp/64bits.htm
(8200 words)
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| | zseries |
| | XA extended the 24 bit 370 architecture to 31 bits (and it brought with it certain problems which, unbelievably, plague us to this day). | | | Of course 64 bit architectures are not new, Compaq (or Digital as it was then) released the 64 bit Alpha chip back in the early 90s, and the proprietary Unix vendors are no strangers to them either. | | | Well in many cases, the answer might very well be hardly anything at all, especially given that the 64 bit support relates to REAL storage support rather than VIRTUAL storage support. |
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http://www.aig.qc.ca/mvs/zseries.html
(544 words)
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| | trace_jpeg.c |
| | The Huffman code can be up to 16 bits long and temp2 can be up to 15 bits for a total of 31 bits. | | | dims[0] = nval; return 1; } /*------------------------------------------------------------------------- */ int huff_table_gen(freqin, nf, bits, huffval, nval) unsigned char bits[], huffval[]; int freqin[], *nval, nf; /* nf ( | | | > jq); } /*printf("16 bit candidate in slow decode = %#x\n", temp);*/ k = 7; nb = 8; /* here nb is code size - 1 */ while ((ks =(temp >> k)) > dc_maxcode[nb]) { k--; nb++; if (k |
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http://sohowww.nascom.nasa.gov/solarsoft/packages/ana/sources/trace_jpeg.c
(1412 words)
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| | United States Patent Application: 0040091271 |
| | If there are any bit errors (i.e., one or more of the bits do not match) (step 330--Yes), the results of the comparison (e.g., the number of bit errors) along with the delay value of the programmable delay 30 are stored as part of the measurement data 142 (step 332). | | | This data is typically a seed value for the generation of a bit sequence, but may be other data as well. | | | The system of claim 31, wherein the external device is a computer. |
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http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=/netahtml/PTO/srchnum.html&r=1&f=G&l=50&s1="20040091271".PGNR.&OS=DN/20040091271&RS=DN/20040091271
(8679 words)
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| | Padding and Bijection |
| | If the blocksize were 32 bytes, we would instead append 31-(xx mod 32) bytes of padding, followed by 3 bits of padding, followed by a 5 bit number indicating the number of complete bytes of padding. | | | Assume bytes are 8 bits each, and the cipher blocksize is 16 bytes (those are what I'd left as parameters). | | | It appears to be an extension of John Savard's scheme of padding out a stream of bits to an 8-bit block boundary to cope with arbitrary block sizes (though these are limited to byte boundaries, not doubt for practical reasons). |
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http://www.ciphersbyritter.com/NEWS6/PADDING.HTM
(8679 words)
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| | RE: ACprof: 28-bit restriction on OID components |
| | > > This makes sense to me. OID parts that are >31 bits impose > two types of > overhead: code overhead so that the program can read/create > the bit string, > and storage overhead. | | | The AC spec can strongly suggest > against >31 bit > values and give the reason of storage overhead, but all > processing programs > must be able to handle them. | | | The limitations on OIDs should be those that > >are in the OID standard, and no others. |
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http://www.imc.org/ietf-pkix/old-archive-00/msg00421.html
(8679 words)
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| | ham.4th |
| | In the stack comment, "" is read as "or.") 11 BYTES FOR FRED 35 CELLS FOR JOAN 17 DOUBLES FOR JOHN 213 PUT 3 FRED (stores 213 in byte 3 of FRED) GET 31 JOAN (retrieves contents of cell 31 of JOAN) 3142352. | | | 0 ndx -- datum) COUNT ?DUP (nonzero = numbers; 0 = bits) IF DUP >R (save type) ROT * + R> 1- 2* ROT IF STORES ELSE FETCHES THEN + @ EXECUTE ELSE ROT (action flag: 1 = store, 0 = fetch) IF ROT ?DUP (nonzero means 1 bit or toggle) IF 0 | | | 0 ndx -- datum) >TYPE COUNT ?DUP (nonzero = numbers; 0 = bits) IF DUP >R (save size) ROT * + R> 1- 2* ROT IF STORES ELSE FETCHES THEN + @ EXECUTE ELSE ROT (action flag: 1 = store, 0 = fetch) IF ROT ?DUP (nonzero means 1 bit or toggle) IF 0 |
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http://www.complang.tuwien.ac.at/forth/ftp.dei.isep.ipp.pt/pub/forth/various/ham.4th
(984 words)
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| | Primary rate interface |
| | Bit robbing procedure is applied for this purpose.There is another code used like Bipolar 8 Zero Substitution for ensuring enough alternatting.In this code if there is more then 8 zeros consequent the pattern 00011011 replaces it.Of course there are code violation replacing in 4-th and 7-th bits. | | | The 1.544 Mhz PRI uses alternating mark inversion(AMI) signaling.0 bits are represented by the absence of voltage on the line and 1 bits are represented by voltage puses with alternating polarity. | | | The 2.048Mhz PRI multiplexes 32 channels.Time slot0 is reserved for physical layer synchronization and signaling.Time slots 1 through 15 and 17 through 31 are used for B channels.Time slot 16 is used for D-channels for network signaling. |
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http://www2.rad.com/networks/1994/isdn/pri.htm
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| | Robbed bit signaling - Wikipedia, the free encyclopedia |
| | Although only one bit out of 48 is robbed, there is no way to know which frames will be robbed by the various T1 connections in a phone conversation, so the signal to noise ratio will be somewhere between 31 and 37 dB. | | | At 56 kbit/s, a voice channel has a signal to noise ratio of 31 dB. | | | Robbed Bit Signalling (RBS) is a specific type of Channel Associated Signaling in use in North America on T1 trunks, and perhaps elsewhere in the world. |
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http://en.wikipedia.org/wiki/Bit_robbing
(381 words)
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| | Re: ACprof: 28-bit restriction on OID components |
| | >>>>> "Charles" == Charles W Gardiner writes: Charles> At 11:39 AM 3/15/2000 +0000, Stephen Farrell wrote: >> Hi James, >> >> If no one else objects then I'd be ok with 31 bits which caters >> for 9 decimal digits fine (32 bits potentially gets into signed >> int muck, esp with Java). | | | It's just a string of bytes -- and Charles> storage is pretty cheap now. |
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http://www.imc.org/ietf-pkix/old-archive-00/msg00419.html
(381 words)
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| | Rantingprofs: BLOGGER QUOTED IN BIT TIME MAGAZINE ARTICLE |
| | May 31, 2004 06:38 AM Post a comment | | | Listed below are links to weblogs that reference BLOGGER QUOTED IN BIT TIME MAGAZINE ARTICLE : | | | Rantingprofs: BLOGGER QUOTED IN BIT TIME MAGAZINE ARTICLE |
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http://rantingprofs.typepad.com/rantingprofs/2004/05/blogger_quoted_.html
(381 words)
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| | CG 6100C Installation and Developer's Manual (60041-18): Framing |
| | Six of the bits are used for a cyclic redundancy check (CRC), to detect errors. | | | Since timeslot 16 can carry only 8 bits of information per frame, it is not possible to send the signaling for all 30 channels in each frame. | | | In each frame, channels are numbered 0 through 31. |
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http://www.nmscommunications.com/manuals/60041-18/framing.html
(557 words)
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| | Online Currents - 2000 Index |
| | Johnstone, Pamela (author), (16:1) 36, (16:2) 29, (16:3) 32, (16:4) 8, (16:4) 30, (16:5) 24, (16:6) 33, (16:8) 33, (16:10) 31 | | | Embase.com advertisement for, (16:3) 36, (16:6) 36 version 2.1 released, (16:1) 28 | | | Lexis-Nexis casual access to, (16:10) 4 Fairfax newspaper content on, (16:10) 25 and NAICS codes, (16:1) 36 Nexis.com, (16:1) 37, (16:4) 30, (16:8) 28 |
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http://www.onlinecurrents.com.au/2001Index.html
(557 words)
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| | Overflow and Negative Integers |
| | For example, on 32 bit computers, a and m are often 31 bits long, as the most significant bit (the 32nd bit) is generally used to indicate sign. | | | When two 31 bit integers are multiplied together, a possibly 62 bit integer results. | | | However, if the result of the multiplication is so as to have the most significant bit (the 32nd bit) set, then the computer may treat this as a negative integer, which is incompatible with the algorithm above. |
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http://csep1.phy.ornl.gov/CSEP/RN/NODE15.html
(310 words)
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| | juniper-nsp: RE: [j-nsp] Does Juniper support RFC 3021 (31-Bit |
| | juniper-nsp: RE: [j-nsp] Does Juniper support RFC 3021 (31-Bit | | | RE: [j-nsp] Does Juniper support RFC 3021 (31-Bit prefixes on p2p links) | | | Subject: [j-nsp] Does Juniper support RFC 3021 (31-Bit prefixes on p2p |
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http://puck.nether.net/lists/juniper-nsp/0348.html
(310 words)
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| | Pantek - Expert Linux and Open Source Services: : RFC #3021: Using 31-Bit Prefixes on IPv4 Point-to-Point Links. A. Retana, R. |
| | Standards Track [Page 3] RFC 3021 31-Bit Prefixes on IPv4 Links December 2000 (b) the link local (or limited) broadcast {-1, -1} {0, 0} The {0, 0} form of a limited broadcast is obsolete, but may still be present in a network. | | | Standards Track [Page 6] RFC 3021 31-Bit Prefixes on IPv4 Links December 2000 In a point-to-point link with a 31-bit mask, the configuration of such a mask SHOULD allow for the generation of datagrams addressed to { , 0 }. | | | Furthermore, the communication between peers is done using multicast, limited broadcast or unicast addresses (all on the local network), none of which are affected with the use of 31-bit subnet masks. |
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http://www.pantek.com/library/general/rfc/rfc3021.html
(310 words)
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| | Method and apparatus for performing DSV protection in an EFM/EFM+ encoding same - US Patent 6778104 |
| | The DSV calculator 31 is used to calculate the DSV of the modulated bit sequence outputted by the EFM/EFM+ modulator 21. | | | Preferably, a segment of the modulated bit sequence that has an odd (or even) number of binary ONEs is adjusted to have an even (or odd) number of binary ONEs. | | | The method as claimed in claim 1, wherein, in step b), a segment of the modulated bit sequence which has an odd number of binary ONES is adjusted so as to have an even number of binary ONEs. |
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http://www.patentstorm.us/patents/6778104.html
(310 words)
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| | MIPS R32 Instructions |
| | The contents of the low-order 32-bit word of GPR rt are shifted right, duplicating the sign-bit (bit 31) in the emptied bits; the word result is placed in GPR rd. The bit-shift amount is specified by the low-order 5 bits of GPR rs. | | | The 32-bit word value in GPR rt is subtracted from the 32-bit value in GPR rs and the 32-bit arithmetic result is and placed into GPR rd. No integer overflow exception occurs under any circumstances. | | | The 32-bit word value in GPR rt is added to the 32-bit value in GPR rs and the 32-bit arithmetic result is placed into GPR rd. No Integer Overflow exception occurs under any circumstances. |
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http://www.cs.uwm.edu/~cs215/TAL_instructions.html
(3522 words)
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| | z/OS Bimodal Migration Accommodation offering |
| | It is expected that there should be very few situations where you'll need to fall back to 31-bit mode, but we're glad to provide this "safety net" to you to assist in your migration plans to move forward to z/OS. | | | This offering gives you the security of knowing you can return to 31-bit mode if there are any 64-bit issues during your migration. | | | IBM is providing the z/OS Bimodal Accommodation offering in response to your requests for an alternative to running in 64-bit mode when first migrating to z/OS 1.2, 1.3, or 1.4 on a z/Architecture server (z800, z890, z900, z990, or equivalent). |
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http://www-1.ibm.com/servers/eserver/zseries/zos/installation/bimodal.html
(453 words)
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| | LinuxElectrons™ - SUSE Service Pack paks New Features |
| | Service Pack 3 delivers state-of-the-art, quality-assured Linux technology for all hardware platforms supported by SUSE LINUX Enterprise Server 8 – x86, Itanium2 processor family, AMD64 with support for 32-bit and 64-bit systems of various manufacturers, IBM iSeries, IBM pSeries, IBM S/390 (31 bit), and IBM zSeries (31 bit and 64 bit). | | | The latest x86 hardware, which had not already been introduced to the market when SUSE LINUX Enterprise Server 8 was released in November 2002, is now supported with improved hyperthreading and ACPI, numerous updated device drivers, and new PCI device detection lists. | | | “SUSE LINUX is committed to getting to our customers the most advanced Linux technology available,” said Holger Dyroff, general manager, Americas, SUSE LINUX. |
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http://www.linuxelectrons.com/article.php?story=20031126210048100
(453 words)
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| | 64 bit 66 Mhz PCI Bus |
| | As we said before, data and addressing are multiplexed over the same pins, either AD[31::00] for 32 bits or AD[31::00] and AD[64::32] for 64 bits. | | | Since the OS plays a huge role in system performance by addressing and transferring data to and from memory, when the OS supports only 32-bits when the hardware supports 64 bits, the system is still somewhat limited. | | | We have tested HP's implementation of 64 bit PCI bus for their Gigabit Ethernet on HP/UX 11.0 with L Class box. |
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http://www.compute-aid.com/64bitpci.html
(453 words)
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| | monthpdf_200504 |
| | They told her that she) Tj ET BT 31.19 430.70 Td (was violating the puppy mill laws for the state, and she needed to either send some dogs to new homes, or that they) Tj ET BT 31.19 419.36 Td (would do it for her. | | | She told me,) Tj ET BT 31.19 612.11 Td ("Sometimes I just wish that Jesus would come soon." I think that this is the correct response for Christians to have.) Tj ET BT 31.19 589.44 Td (Thanks to Adam and Eve, there is neither completeness \(shalam\) nor peace \(shalom\). | | | He doesn't know how) Tj ET BT 31.19 305.97 Td (to play yet, because he spend almost all of his life in a cage, and when he got out he was with other "cage-bound" dogs) Tj ET BT 31.19 294.63 Td (that didn't know how to behave out of a cage. |
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http://www.kypackrat.com/plugin/monthpdf_200504
(5798 words)
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| | clist75.html |
| | The primary message here is that when you migrate to z/OS on a zSeries machine, your applications do not need to be changed, because their 24-bit and 31-bit modes are fully supported. | | | Therefore, there are no addressing mode compatibility issues for applications that run in either 24-bit or 31-bit addressing mode when running under z/Architecture. | | | z/Architecture - This is the hardware architecture designed into zSeries machines that supports the following facilities: 64-bit mode addressability (both real and virtual), HiperSockets, Intelligent Resource Director (IRD) and IBM's License Manager (ILM - which has now been dropped). |
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http://www.watsonwalker.com/clist75.html
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| | MeasureIT - Issue 5.0 - Book Review: Stephen L. Samson's 'MVS Performance Management' by Linwood Merritt |
| | The author takes his readers through the introduction of Virtual Storage, multiprocessing, 24-bit and 31-bit addressing, Parallel Sysplex, and the latest z/Architecture. | | | Of particular interest to this reviewer was chapter 6, "z/Architecture, zSeries, and z/OS." This chapter discusses the 2-gigabyte limitation of 31-bit addressing and the implementation of 64-bit addressing in z/OS. | | | In his description of z/Architecture, the author discusses 64-bit registers, real and virtual storage addressing, Dynamic Address Translation, page structures, architecture modes, and multiple channel subsystems. |
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http://www.cmg.org/measureit/issues/mit05/m_5_2.html
(541 words)
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| | Ittiam Products Voiceband Modems V.90 |
| | synchronous channel data signaling rates in the upstream direction from 4800 bit/s to 28 800 bit/s in increments of 2400 bit/s, with optional support for 31 200 bit/s and 33 600 bit/s; | | | synchronous channel data signaling rates in the downstream direction from 28 000 bit/s to 56 000 bit/s in increments of 8000/6 bit/s; | | | exchange of rate sequences during start-up to establish the data signaling rate; |
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http://www.ittiam.com/pages/products/v90.htm
(183 words)
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| | 536 |
| | 00000420 C36 DATA NP/2/, IW/31/ 00000430 C36 DATA AC(1,1),AC(2,1)/O000000000000,O000000000001/, 00000440 C36 * AC(1,2),AC(2,2)/O777777777777,O777777777641/, 00000450 C36 * AC(1,3),AC(2,3)/O777777777777,O777777777603/, 00000460 C36 * AC(1,4),AC(2,4)/O777777777777,O777777777573/, 00000470 C36 * AC(1,5),AC(2,5)/O777777777777,O777777777636/, 00000480 C36 * AC(1,6),AC(2,6)/O777777777777,O777777777402/ 00000490 C 00000500 C.60......CDC 6600/7600 60-BIT +-, 48-BIT */, OCTAL CONSTANTS(B). | | | 00000510 C60 DATA NP/2/, IW/31/ 00000520 C60 DATA AC(1,1),AC(2,1)/00000000000000000000B,00000000000000000001B/,00000530 C60 * AC(1,2),AC(2,2)/00000000777777777777B,00000000777777777641B/,00000540 C60 * AC(1,3),AC(2,3)/00000000777777777777B,00000000777777777603B/,00000550 C60 * AC(1,4),AC(2,4)/00000000777777777777B,00000000777777777573B/,00000560 C60 * AC(1,5),AC(2,5)/00000000777777777777B,00000000777777777636B/,00000570 C60 * AC(1,6),AC(2,6)/00000000777777777777B,00000000777777777402B/ 00000580 C 00000590 WRITE(6,1) 00000600 C32 1 FORMAT(45H1HEXADECIMAL INPUT(X) HEXADECIMAL OUTPUT(FX)/1X) 00000610 C36 1 FORMAT(15H1OCTAL INPUT(X),14X,16HOCTAL OUTPUT(FX)/1X) 00000620 C60 1 FORMAT(15H1OCTAL INPUT(X),14X,16HOCTAL OUTPUT(FX)/1X) 00000630 C---------INPUT AND ENCIPHER 10 BIT STRINGS. | | | C-------------- SAMPLE PROGRAM TO ENCIPHER 72-BIT PASSWORDS ACROSS 00000010 C MACHINES WITH 3 DIFFERENT WORD SIZES. |
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http://www.netlib.org/toms/536
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