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| | Message Passing Interface (MPI) |
 | | Message Passing Interface: A specification for message passing libraries, designed to be a standard for distributed memory, message passing, parallel computing. | | | April, 1992: Workshop on Standards for Message Passing in a Distributed Memory Environment, sponsored by the Center for Research on Parallel Computing, Williamsburg, Virginia. | | | In distributed memory systems, data is generally sent as packets of information over a network from one processor to another. |
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http://torvalds.cs.mtsu.edu/~rbutler/courses/pp6/www.llnl.gov/computing/tutorials/workshops/workshop/mpi/MAIN.html
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| | Message Passing Interface (MPI) Lab |
| | Write a program which sums all the processor numbers by connecting the processors in a ring and passing the processor numbers around the ring, summing them as they go. | | | The MPI implementation that we will be using is called MPICH (it is based on an earlier portable message passing language called Chameleon, hence the name MPICH). | | | Look at an example program when you are finished, or if you get stuck. |
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http://www.dhpc.adelaide.edu.au/education/dhpc/lab/MPI/MPIlabnew1.html
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| | The Message Passing Interface (MPI) |
| | A list of links to web pages related to the code implementing or utilising the Message Passing Interface for parallel computing. | | | Includes CHIMP, an early message passing library upon which an MPI interface has been added and implementations of MPI for a number of specialised platforms including the Cray T3D. | | | MPICH can run on individual multi-processor machines, using shared memory to communicate, or on arrays of machines, communicating via the network. |
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http://www.env.leeds.ac.uk/~jason/MPI
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| | NTNU HPC Project - MPI |
| | MPI is a standard message passing programming interface for MIMD distributed memory concurrent computers, developed by the Message Passing Interface Forum (MPIF). | | | The file token.c application contains source which pass a token around, increment it by the processor count and output to file | | | The final report, Version 1.0, of the MPIF, was released on May 5, 1994 and is available as a 220 page postscript document. |
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http://hpc.ntnu.no/software/mpi.html
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| | 395800.1990-1992 |
| | Processor engine modules including a bus, a processor, an interface controller, a shared dual port RAM, and a shared RAM controller are horizontally and/or vertically integrated at multiple levels without major restructuring of the composite system control operations by having each slave processor engine module interface as a peripheral upon the bus of its master. | | | When a given data processor wishes to send a message to another data processor, it transfers the message to its communication processor which in turn transfers the message to the communication processor coupled to one of these 6 ports with information specifying the final destination of the message. | | | The Scientific Processor is under task assignment control of the host processor and shares the same memory space as the host processor, and thereby provides the tight coupling without need of dedicated memory or caching. |
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http://lpf.ai.mit.edu/Patents/abstracts/395800.1990-1992
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| | Patent 4488289: Interface facility for a packet switching system |
| | An important function of the trunk controller is to interface with the packet switching network and the central computer or processor, during a packet message set-up procedure at the beginning of a packet call. | | | Packets from switching network 116 are received by input circuit 1406 via switch interface 1418. | | | Packets are transmitted between the access line controllers and the resident interfaces using standard packet protocols which define three virtual channels for communication between the resident interface and the access line controller. |
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http://www.freepatentsonline.com/4488289.html
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| | Glossary of terms |
| | Message passing: Style of parallel programming for distributed memory systems in which non-local data that is required explicitly must be transported to the processor(s) that need(s) it by appropriate send and receive messages. | | | MPI: A message passing library, Message Passing Interface, that implements the message passing style of programming. | | | Presently MPI is the de facto standard for this kind of programming. |
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http://www.phys.uu.nl/~steen/web01/glossary.html
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| | Virtual machine - Wikipedia, the free encyclopedia |
| | PVM (Parallel Virtual Machine) and MPI (Message Passing Interface) are two common software packages that permits a heterogeneous collection of Unix and/or Windows computers hooked together by a network and used as a single large parallel computer. | | | Virtual machines can also perform the role of an emulator, allowing software applications and operating systems written for another computer processor architecture to be run. | | | In general terms, a virtual machine in computer science is software that creates a virtualized environment between the computer platform and the end user in which the end user can operate software. |
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http://en.wikipedia.org/wiki/Virtual_machine
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| | Running beowulf software on cheap risc processors |
| | Previous message: Running beowulf software on cheap risc processors | | | > The SH-4 processor comes with a built-in PCI interface so the > chip count will be low. | | | Next message: Running beowulf software on cheap risc processors |
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http://www.beowulf.org/pipermail/test/1999-September/007631.html
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| | IPMI (Intelligent Platform Management Interface) |
| | IPMI is a message-based hardware management interface that is implemented at the silicon level and uses a baseboard management controller, which is a small processor that sets up IPMI as a subsystem independent of the server's CPU or operating system. | | | IPMI can be exposed through any standard management software interface such as Common Information Model, SNMP and Windows Management Instrumentation. | | | A specification, developed by Dell, HP, Intel and NEC, that defines interfaces for use in monitoring the physical health of servers, such as temperature, voltage, fans, power supplies and chassis. |
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http://www.networkworld.com/details/6199.html
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| | Compaq Computer Japan's Scalar Supercomputer System up and running at Keio University |
| | The system consists of two machines: a high-end SMP (Symmetrical Multi-processor) server based on the NUMA (Non Uniform Memory Access) architecture, and a 1U MPI (Message Passing Interface) server. | | | The multithreaded SMP parallel server is comprised of an AlphaServer GS320 high-performance server equipped with 32 64-bit 1GHz Alpha21264 processors and 64GB of main memory, and an AlphaServer GS160 server embedded with 16 of the Alpha21264 processors and 16GB of memory, and runs Tru64 Unix as an operating system. | | | Tokyo 27 December 2001 The massively parallel computing system of Compaq Japan is now up and running at the Information Technology Center (ITC) of Keio University. |
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http://www.hoise.com/primeur/02/articles/monthly/AE-PR-02-02-4.html
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| | Channel interface circuit providing virtual channel number translation and direct memory access - Patent 4419728 |
| | The subject channel interface circuit is programmable and serves to dynamically translate the header portion of the data message as it is being received from a virtual address into a hardware memory address, which is used to activate a specific location in the processor memory. | | | Thus, once a virtual channel number has been selected for a particular processor-to-processor intercommunication, such information is included in the header of the data message, and the entire data message is stored in processor memory 102 in the reader/writer queue that is used for outgoing data messages. | | | This access is accomplished by processor 101 outputting on communication channel 120, a data message containing the address of the destination processor and a virtual channel number of zero, which indicates to the destination processor that this is an initial communication setup message intended for the destination processor. |
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http://www.freepatentsonline.com/4419728.html
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| | Patent 4419728: Channel interface circuit providing virtual channel number translation and direct memory access |
| | Channel interface circuit 100 monitors communication channel 120 to determine whether one of these data messages is destined for processor memory 102. | | | Thus, once a virtual channel number has been selected for a particular processor-to-processor intercommunication, such information is included in the header of the data message, and the entire data message is stored in processor memory 102 in the reader/writer queue that is used for outgoing data messages. | | | This access is accomplished by processor 101 outputting on communication channel 120, a data message containing the address of the destination processor and a virtual channel number of zero, which indicates to the destination processor that this is an initial communication setup message intended for the destination processor. |
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http://www.freepatentsonline.com/4419728.html
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| | Electronic mail system with RF communications to mobile processors and method of operation thereof - Patent 5436960 |
| | The interface switch connects an electronic mail system and/or at least one additional processor to a RF data transmission network which transmits the information to a RF receiver which is connectable to the destination processor to transfer the received RF message from the RF receiver to the destination processor. | | | The electronic mail system or the interface switch may append the identification number of the RF receiver to receive the information which is utilized by the RF information transmission network to determine the final destination of the RF receiver to which the message is broadcast by the RF information transmission network. | | | The originated information is transmitted to a receiving interface switch by the electronic mail system in response to an address of the receiving interface switch and the originated information is transmitted from the receiving interface switch to the RF information transmission network with an address of the destination processor to receive the information. |
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http://www.freepatentsonline.com/5436960.html
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| | ARPANET IMP, Interface Message Processor |
| | The Interface Message Processor provided a system independent interface to the ARPANET that could be used by any computer system, which opened the Internet network architecture from the very beginning. | | | The idea for the Interface Message Processor (IMP) was suggested by Wesley Clark at the "ARPANET Design Session" held by Lawrence Roberts at the IPTO Principal Investigator meeting in Ann Arbor Michigan in April, 1967. | | | Because they were based in Cambridge in his home state of Massachusetts, then Senator Ted Kennedy sent BBN a well-meaning but slightly confused telegram of congratulations for winning a contract to develop an "interfaith message processor". |
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http://www.livinginternet.com/i/ii_imp.htm
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| | Information distribution system - Patent 5247575 |
| | The message can be a standard notice requesting that the customer call the accounting department, or a message tailored by the accounting processor 60 to the individual account by reference to the billing information stored in the accounting register 62. | | | The message stored in the main memory 50 is then communicated to the customer through the facsimile converter 54 or the RS-232C interface 56 shown in FIG. | | | According to a still further feature of the present invention, the system includes a telephone line interface, a third storage device and a device for calling a remote host computer via the telephone line interface and requesting transfer of selected information from that host computer to the third storage device. |
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http://www.freepatentsonline.com/5247575.html
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| | Switched virtual circuit call processing/routing system - US Patent 6816483 |
| | Generally, a request for a circuit will be routed through call processing message pipe 92A and call processor interface 144 to switched circuit manager 140. | | | The first software process uses the message path to request the switched virtual circuit between the node and the wide-area-network destination, and the second software process uses the message path to notify the first software process when the switched virtual circuit has been established. | | | Circuit 32 is removed by the VNS that created it, and a call release message is sent from VNS 34 through the signaling channel to the other PBX and its end user. |
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http://www.patentstorm.us/patents/6816483.html
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| | IBM Linux cluster systems fundamentals - SPMD job example |
| | This example uses MPI SPMD (Message Passing Interface-standard Single Processor Multiple Data structures) to sum a set of 1,000,000 exponentials. | | | The Message Passing Interface is a standardized programming paradigm for parallel computers designed to allow separate processes to efficiently communicate with each other via messages. | | | SPMD parallel job example using MPI-standard message passing |
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http://www.scd.ucar.edu/docs/lightning/examples/mpi.html
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| | NASA Tech Briefs: SpaceWire driver software for special DSPs |
| | The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. | | | A computer program provides a highlevel C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). | | | In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). |
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http://findarticles.com/p/articles/mi_qa3957/is_200303/ai_n9205849
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| | SGI - Press Releases: SGI Altix 3000 Screams on Upcoming Itanium 2 'Madison' Processor Running 64-bit Technical Applications |
| | The impressive performance results reported from running Amber and STAR-CD on the Madison processor were achieved by using SGI® Message Passing Toolkit (MPT), the highly tuned SGI message passing interface (MPI) library that provides versions of industry-standard message-passing libraries optimized for SGI systems. | | | SGI is poised to ship Altix 3000 systems with supported supercluster configurations of 4 to 128 Madison processors as soon as the new processors are commercially available. | | | Current evidence indicates that these numbers are not expected to vary much when applied to the new POWER4+™ processor. |
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http://www.sgi.com/company_info/newsroom/press_releases/2003/may/madison.html
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| | BYTE.com |
| | The second ServerNet component is a processor-interface chip, which is implemented as an ASIC. | | | Finally, you can use ServerNet to build a fault-tolerant server by connecting two duplicate systems through the dual ports of the processor-interface ASICs. | | | SMP servers can use ServerNet routers and peripheral-interface ASICs to provide scalable I/O (e.g., increasing the number of Ethernet connections or boosting disk storage) without degrading the performance of the OS or applications software. |
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http://www.byte.com/art/9607/sec12/art1.htm
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| | Patent 5708657: Apparatus for interfacing mobile switching center(MSC) with base station controller(BSC) of CDMA mobile system |
| | The control signal for processing the call is accomplished by using the inner communication message protocol which is connected in the EIA-422 interfacing mode to the call control processor of the base station controller. | | | A base station controller interface of the CDMA mobile switching center as in claim 1, wherein each of the nodes of said local subsystem network is accompanied with the signal for transmitting the TD-bus in triplicate. | | | The subordinate processor performs the control of the device by receiving all of the control signals from the access switching processor through the local subsystem network, or is the controlling processor which functions to transmit in the IPC form the device condition through the local subsystem network. |
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http://www.freepatentsonline.com/5708657.html
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| | A Brief History of the Internet |
| | When Senator Ted Kennedy heard in 1968 that the pioneering Massachusetts company BBN had won the ARPA contract for an "interface message processor (IMP)," he sent a congratulatory telegram to BBN for their ecumenical spirit in winning the "interfaith message processor" contract. | | | Since commercial usage was so widespread by this time and educational institutions had been paying their own way for some time, the loss of NSF funding had no appreciable effect on costs. | | | The Internet was the result of some visionary thinking by people in the early 1960s who saw great potential value in allowing computers to share information on research and development in scientific and military fields. |
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http://www.walthowe.com/navnet/history.html
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| | AT$T 5ESS(tm) From Top to Bottom |
| | COMMUNICATIONS MODULE Message Switch (MSGS) - Provides for control message transfer between the 3B20D Processor and Interface Modules (IM's) - Contains the clock for synchronizing the network. | | | The 5ESS network is a TST (Time Space Time) topology, the TSIs (Time Slot Interchangers) each have their own processor, this makes the 5ESS one of the faster switches. | | | NOTE: Order IM-5D000-01 (5ESS input manual) or OM-5D000-01 (5ESS output manual) for more information on this and other messages from the CIC at 1-800-432-6600. |
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http://www.nerdsrus.com/uswest/ess/ess05.htm
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| | Telex 80 |
| | Once written, the telex message is transferred to the Telex 80 box, which automatically transmits the message to the previously entered number on one of the telex linies. | | | When using Telex 80 each user can enter into dialog and it is possible to have as many simultaneous dialogs as there are telex interfaces in the Telex 80. | | | Hence you can start with the smallest System 2 with 1 telex line interface and up to 5 terminal interfaces and field upgrade it up to 4 telex line interfaces, I teletex interface and 8 terminal interfaces. |
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http://www.microapplication.dk/telex80.htm
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| | OAM Software Jumps into the Terabit Realm |
| | Note that a response for an OAM request (message 4) carries the processor utilization of the network interface card so that the other part of the OAM request broker can intelligently distribute the next OAM request as far as processor utilization at the network interface cards is concerned. | | | In the context of OAM software for terabit switching, this means that when increased traffic causes the capability of the switch to be upgraded, the OAM software can scale up automatically to handle the additional network management traffic generated by external users and switch resources. | | | For example, the pre-condition logic of an OAM Set request to turn the administration status of a port to the DOWN status can be to verify whether there is any ongoing traffic in any virtual circuits of the port. |
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http://www.commsdesign.com/printableArticle?articleID=16502647
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| | Encyclopedia: DragonFlyBSD |
| | Threads are never preemptively switched from one processor to another; they are only migrated by the passing of an "Interprocessor Interrupt" (IPI) message between the CPUs involved. | | | In DragonFly, threads are locked to CPUs by design, and each processor has its own LWKT scheduler. | | | In order to run safely on multiprocessor machines, access to shared resources (files, data structures etc.) must be serialized so that threads or processes do not attempt to modify the same resource at the same time. |
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http://www.nationmaster.com/encyclopedia/DragonFlyBSD
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| | Preview |
| | The latest documents will describe different facets of the Cell microprocessor such as; Cell Broadband Engine Architecture, Synergistic Processor Unit Instruction Set Architecture (SPU ISA), SPU C/C++ Language Extensions, Application Binary Interface and Assembly Language specifications. | | | The Cell Broadband Engine Architecture defines a processor structure, which is directed towards multimedia applications and distributed processing. | | | The SPU ISA describes the high-performance SIMD RISC processor, which speeds-up streaming and media applications based on the Cell Broadband Engine Architecture. |
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http://www.techtree.com/techtree/jsp/article.jsp?article_id=5651&cat_id=581
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| | Interior Gateway Protocol from FOLDOC |
| | Nearby terms: Interface Definition Language « Interface Description Language « Interface Message Processor « Interior Gateway Protocol » interlace » interlaced image » interlacing | | | (IGP) An Internet protocol which distributes routing information to the router s within an autonomous system. | | | The term " gateway " is historical, "router" is currently the preferred term. |
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http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?IGP
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