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| | random access memory - definition of random access memory in Encyclopedia |
 | | This is in contrast to sequential memory devices such as magnetic tapes, discs and drums, in which the mechanical movement of the storage medium forces the computer to access data in a fixed order. | | | Core memory, which used wires attached to small ferrite electromagnetic cores, also had roughly equal access time (the term “core” is still used by some programmers to describe the RAM at the heart of a computer). | | | Random Access Memory or RAM is a type of computer storage whose contents can be accessed in any order. |
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http://encyclopedia.laborlawtalk.com/random_access_memory
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| | Cache Coherent Non Uniform Memory Access (ccNUMA) Support |
| | Access from a processor to node local memory is fast, as is the case with small SMP systems. | | | Access to memory in other nodes is slower. | | | The use of fine-grained interleaving, in which the memory is interleaved across the nodes at a small granularity, is mutually exclusive with respect to ccNUMA optimizations. |
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http://msdn.microsoft.com/library/en-us/appendix/hh/appendix/enhancements5_0dd92ce5-8ca1-4956-b7ad-8d8272239a93.xml.asp
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| | brecht.txt |
| | While these previous studies investigate the importance of scheduling techniques for reducing the number of non-local memory accesses by co- locating processes with the data being accessed, our work investigates the importance of scheduling techniques for reducing the cost of required non-local memory accesses in environments where processes and data cannot be co-located. | | | This results in systems with a number of levels in the memory hierarchy and memory access latencies that vary with the number of levels of the hierarchy that must be traversed. | | | Increasing Memory Latencies The NUMAness of a system can be thought of as the degree to which memory access latencies are affected by the distance between the requesting processor and the desired memory location. |
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http://www.usenix.org/publications/library/proceedings/sedms4/full_papers/brecht.txt
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| | 36514.000622&ELEMENT_SET=DECL |
| | Such computer systems are said to have a non- uniform memory access because each processor has lower access latency with respect to data stored in the system memory at its local node than with respect to data stored in the system memory at a remote node. | | | NUMA systems can be further classified as either non-coherent or cache coherent, depending upon whether or not data coherency is maintained between caches in different nodes. | | | The complexity of cache coherent NUMA (CC-NUMA) systems is attributable in large measure to the additional communication required for hardware to maintain data coherency not only between the various levels of cache memory and system memory within each node but also between cache and system memories in different nodes. |
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http://www.wipo.int/cgi-pct/guest/getbykey5?KEY=00/36514.000622&ELEMENT_SET=DECL
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| | An Overview of MPP Systems |
| | Non Uniform Memory Access systems are those systems in which memory access times are not uniform, but rather dependent on the route to and latency at the node containing the requested memory line. | | | Memory associated to processors in such a way is called local memory from the viewpoint of that processor because it has direct access to that node's memory ports and need not go through any memory network routing. | | | In the NUMA architecture, the memory was distributed among the various processor nodes and memory accesses to the local memory would happen faster than accesses that had to go to memory stored on a remote processor node. |
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http://www.blight.com/~ja-wells/311/report.html
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| | 6.6. Non-Uniform Memory Access (NUMA) Machines |
| | When memory is allocated by the parent, it is distributed among all the nodes in a round-robin fashon using a stride of MAXLMD. | | | The goal for optimal programming of NUMA machines is to maximize references to local memory on the node while minimizing references to remote memory. | | | One design goal of a NUMA machine is to make the routers as fast as possible to minimize the difference between local and remote memory references. |
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http://www.fmslib.com/fmsman/doc/numa.html
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| | Parallel Hardware Architecture |
| | In uniform disk access systems, or shared disk systems, as shown in Figure 2-2, the cost of disk access is the same for all nodes. | | | In NUMA configurations, the cost of accessing a specific location in main memory is different for some of the CPUs relative to others. | | | CPU - The main processing component of a computer that reads from and writes to the computer's main memory. |
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http://www.usd.edu/oracle/doc/paraserv.817/a76968/pshwarch.htm
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| | NUMA Frequently Asked Questions |
| | NUMA is one way of reducing the number of CPUs competing for access to a shared memory bus. | | | That said, local memory is typically defined to be the memory that is on the same node as the CPU currently running the process. | | | NUMA alleviates these bottlenecks by limiting the number of CPUs on any one memory bus, and connecting the various nodes by means of a high speed interconnect. |
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http://lse.sourceforge.net/numa/faq
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| | Glossary Search Results |
| | NUMA (Non-Uniform Memory Access) - A multiprocessing architecture where each processor or small group of processors has its own group of memory chips. | | | Accessing memory local to the processor is faster than accessing remote memory on other processor boards. | | | NUMA typically scales better than SMP architectures, where memory is all accessed at the same speed in one large bank. |
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http://www.geek.com/glossary/glossary_search.cgi?n
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| | NUMA: Non-Uniform Memory Access |
| | The physically distributed memory of Origin systems implies that access times are no longer uniform, it varies depending on the distance from the memory being accessed. | | | Initial latencies for remote memory accesses are the largest, the added latency for each additional router the data must pass through after the first are negligible. | | | Programs that use the two levels of cache of the R10000 effectively will not exhibit problems due to NUMA effects since a vast majority of memory access are satisfied from cache. |
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http://www.arc.unm.edu/~bbaltz/SGI/ohw_mod/ohw_Slide_22.html
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| | Linux Scalability Effort: NUMA Group Homepage |
| | On NUMA systems, optimal performance is obtained by locating processes as close to the memory they access as possible. | | | For optimal performance, the kernel needs to be aware of where memory is located, and keep memory used as close as possible to the user of the memory. | | | For most processes, optimal performance is obtained by allocating all memory for the process from the same node, and dispatching the process on processors on that node. |
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http://lse.sourceforge.net/numa
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| | IBM Redbooks Introduction to NUMA on xSeries Servers |
| | Every CPU can also access the memory of any other CPU in the system but at longer latency. | | | But by limiting the number of processors that directly access that memory, performance is improved because of the much shorter queue of requests. | | | NUMA effectively means that every processor or every group of processors has a certain amount of memory local to it. |
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http://www.redbooks.ibm.com/abstracts/tips0476.html
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| | Helix Systems Overview |
| | All of the SGI systems use a ccNUMA architecture (cache coherent, non-uniform memory access) to combine the scalability of distributed memory machines with the ease of use of traditional shared memory SMP computers. | | | Helix is a shared memory SMP (symmetrical multiprocessor) computer, meaning that each of its processors has direct access to all of system memory. | | | Nimbus is a shared memory multiprocessor SGI 3400 supercomputer that is used for applications requiring large computational or memory resources. |
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http://helix.nih.gov/systems
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| | Memory Placement on the Origin2000 |
| | Since the Origin2000 is a NUMA (Non-Uniform Memory Access) system, the time it takes for a CPU to access a memory location varies according to the location of the memory relative to the CPU. | | | Remote memory accesses are slower than local memory accesses and hence the user will pay a penalty. | | | The NCSA Origin systems have either 512Mb or 1Gb memory per node (each node has 2 processors), so codes requiring more memory than this should be tuned to run in parallel for best performance. |
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http://www.ncsa.uiuc.edu/UserInfo/Consulting/Tips/Memory_Placement.html
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| | A primer on NUMA (Non-Uniform Memory Access) |
| | Each processor uses the local memory for data and instruction sharing purpose and some of its internal computations are done in the internal local memory which leads to reduced memory contention resulting into higher program efficiency. | | | "NUMA is a memory architecture used in multiprocessors wherein apart from the common system memory each processor has its own local memory which can be used for the processor's own computations. |
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http://rootprompt.org/article.php3?article=6443
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| | numa_intro(3) |
| | NUMA, or Non-Uniform Memory Access, refers to a hardware architectural feature in modern multi-processor platforms that attempts to address the increasing disparity between requirements for processor speed and bandwidth and the bandwidth capabilities of memory systems, including the interconnect between processors and memory. | | | NUMA Enhancements to Basic UNIX Algorithms and Default Behaviors For NUMA, modifications to basic UNIX algorithms (scheduling, memory allocation, and so forth) and to default behaviors maximize local accesses transparently to applications. | | | Topology-aware placement of data The operating system attempts to allocate memory for application (and kernel) data on the RAD closest to where the data will be accessed; or, for data that is globally accessed, the operating system may allocate memory across the available RADs. |
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http://www.helsinki.fi/atk/unix/dec_manuals/DOC_51/HTML/MAN/MAN3/0488____.HTM
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| | AppDev: Something You Should Know by Irena Kennedy |
| | NUMA is a computer memory design used in multiprocessors, where the memory access time depends on the memory location relative to a processor. | | | The optimizer will avoid generating access plans using a hash join if it detects that a low memory situation may occur during query execution. | | | foreign or remote memory), that is, memory which is local to another processor or shared between processors. |
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http://blogs.msdn.com/irenak/default.aspx
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| | Preparing for high-end Windows CNET News.com |
| | The Redmond, Wash.-based software company is working on support for a technology called non-uniform memory access, or NUMA, one method for designing large servers crammed with processors, said Sean McGrane, program manager for Microsoft's top-end Datacenter server. | | | NUMA is named for the fact that it can take different amounts of time to fetch information from memory. | | | Microsoft's support for NUMA defines standard communication channels so software can determine whether it's running on a NUMA machine and, if so, how the server is configured, McGrane said. |
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http://news.com.com/2100-1001-884391.html
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| | NUMA - Enterprise Networking Planet - Practical Advice for Managing Your LANs, WANs, SANs and WLANs |
| | Short for Non-Uniform Memory Access, a type of parallel processing architecture in which each processor has its own local memory but can also access memory owned by other processors. | | | It's called non-uniform because the memory access times are faster when a processor accesses its own memory than when it borrows memory from another processor. | | | NUMA computers offer the scalability of MPP and the programming ease of SMP. |
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http://networking.webopedia.com/TERM/N/NUMA.html
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| | InterSystems Caché - Caché Technology - Technical Documents - Caché Technology Directions - 2002 |
| | NUMA, which stands for Non-Uniform Memory Access, addresses this issue by dividing key hardware elements, such as processors and memory, into "building blocks". | | | A number of hardware vendors (including HP, IBM and Sun) have introduced large-scale computer systems that employ Non-Uniform Memory Access (NUMA) architectures. | | | Because Caché makes extensive use of shared memory (for instance for database buffers) speed of memory access has a direct bearing on Caché performance. |
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http://www.intersystems.com/cache/technology/directions/numa.html
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| | IRAM Class Discussion Mon, Jan 29/96 |
| | Assuming that 20% of instructions reference memory, the "memory wall" is hit when the average time to access memory is 5 CPU cycles. | | | Wulf's suggestion for NUMA as a solution to the memory gap problem, prompted discussion of where NUMA features have appeared in the past. | | | In that sense, memory wasn't really faster, but the instruction fetch time was only a third. |
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http://www.cs.berkeley.edu/~pattrsn/294/lec6.html#Wul95
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| | 4csc5551.doc |
| | A computer in which some locations in shared memory takes no longer to access that others are called as Non-Uniform Memory Access (NUMA). | | | OpenMP is an execution to a sequential programming language to support shared memory MIMD computation. | | | The on-board cache memory responds quickly enough to allow the Intel 80386 CPU to operate at full speed. |
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http://ouray.cudenver.edu/~kvrengan/4csc5551.doc
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| | ccNUMA machines |
| | The most important ways to let the SMP nodes share their memory are S-COMA Simple Cache-Only Memory Architecture) and ccNUMA, which stands for Cache Coherent Non-Uniform Memory Access. | | | On the other hand, because the memory is physically distributed, it cannot be guaranteed that a data access operation always will be satisfied within the same time. | | | So, when data is required that does not reside in the local node's memory it is retrieved from the memory of the node where it is stored. |
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http://www.phys.uu.nl/~steen/web01/ccNUMA.html
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| | Uniformity of shared memory access |
| | : non-uniform memory access - typically exhibited by DSM architecture, memory locations incur different access delays depending on which processor accesses them. | | | : uniform memory access - all processors have equal access time to any given memory location. | | | : the memory consists only of the collective cache contents of the processors and data migrates to the requesting processor. |
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http://www.cs.mu.oz.au/677/notes/node18.html
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| | arch.html |
| | Because of the way the architecture is structured local accesses on different nodes dont interfere with each other and due to the cache local memory accesses are much quicker than remote accesses (note there are typically two levels of cache in a cc-NUMA system.). | | | Although the memory is physically distributed we can still class theses machines as Shared Memory MIMD because a single system has been established by special hardware/software. | | | There is a reduction in access latency and not as much contention for shared data from multiple processors but it introduces a big problem, cache coherence. |
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http://homepage.ntlworld.com/mangald/project/arch.html
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| | 22C:116, Lecture 25, Spring 2002 |
| | Non-Uniform Memory Access in a shared memory multiprocessor implies that all memory is shared, but each CPU has fast access only part of memory, its own local memory, and slower access to other parts of memory, the local memory areas of other CPUs. | | | So long as the memory addresses likely to be used by the process are in the cache, it will run at full speed, but when the cache holds none of the process's memory addresses, the process will run very slowly until the cache is loaded. | | | Modern cache designs allow memory words belonging to multiple processes to reside simultaneously in the cache, so on a uniprocessor, there is a reasonable chance that when a high priority processes is scheduled, it will find that many of the memory references it makes result in cache hits. |
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http://www.cs.uiowa.edu/~jones/opsys/spring02/notes/25.html
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| | ITworld.com - LINUX TIPS AND TRICKS - NUMA |
| | Non-uniform memory access (NUMA)is a relatively new method of configuring a cluster of processors in a multiprocessor system so that they share memory locally. | | | Put differently, NUMA introduces an additional cache layer that reduces the number of accesses to the external memory. | | | NUMA adds an intermediate level of memory shared among a few processors so that most data accesses don't have to travel on the main bus. |
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http://www.itworld.com/nl/lnx_tip/10192001
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| | CASHMERe Home Page |
| | In the context of CASHMERe, early simulation results indicate that NCC-NUMA (Non Cache Coherent Non Uniform Memory Access) machines can greatly improve the performance of DSM systems, and approach that of fully hardware coherent multiprocessors. | | | The basic property of NCC-NUMA systems is the ability to access remote memory directly; such a capability is offered by a variety of network interfaces including DEC's Memory Channel, HP's Hamlyn, the VIA standard, the Scheduled Transfer standard, and the Princeton | | | It is well accepted today that commercial workstations offer the best price/performance ratio and that shared memory provides the most desirable programming paradigm for parallel computing. |
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http://www.cs.rochester.edu/u/kthanasi/cashmere.html
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