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| | About Excalibur Embedded Processor Solutions |
 | | This configurable, general-purpose RISC processor can be easily integrated with user logic and programmed into an Altera FPGA. | | | The processor features a 16-bit instruction set, user-selectable 16- or 32-bit data paths, and a library of standard soft peripherals configurable for a wide array of applications. | | | Both Excalibur devices and the Nios embedded processor are also supported by industry-standard software development tools, debugging solutions, and operating systems support, providing a complete development package for system-on-a-programmable-chip (SOPC) designs. |
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http://www.altera.com/products/devices/excalibur/exc-index.html
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| | Computer History Museum - Timeline |
| | Within a decade, research on the optical transistor led to successful work on the first all-optical processor and the first general-purpose all-optical computer. | | | The first optical data storage disk had 60 times the capacity of a 5 1/4-inch floppy disk. | | | Developed by Philips, the disk stored data as indelible marks burned by a laser that could not be overwritten — making it useful primarily for storing large quantities of information that would never need revision. |
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http://www.computerhistory.org/timeline/timeline.php?timeline_category=cmpnt
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| | Improved Linux* SMP Scaling: User-directed Processor Affinity - Intel® Software Network |
| | Depending on the settings programmed in the I/O APIC, interrupts are distributed either to processor(s) specified in the I/O APIC redirection table or the processor that is executing the lowest priority process. | | | The migrated process needs to warm various levels of data caches in the processor that it has just migrated to. | | | In Linux 2.6, a more intelligent scheme is implemented, where the kernel dispatches interrupts to one processor for a short duration before it randomly switches the interrupt delivery to a different processor. |
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http://intel.com/cd/ids/developer/asmo-na/eng/dc/windows/188935.htm?page=1
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| | PC KITS-tutorial page (ISA BUS) |
| | The DMA (Direct Memory Access) controller borrows the address bus, the data bus and the control bus from the system and transfers a programmed series of bytes from a fast I/O device to the memory. | | | When the data transfer is completed unasserts the HRQ signal and the processor gets the control of the buses again. | | | On the contrary the ISA BUS outputs a 20 bit address bus and a 8 bit data BUS. |
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http://www.ctv.es/pckits/tISA.html
(1206 words)
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| | Communication system between local area network stations - Patent 6272210 |
| | said current generator being connected to said data processor when said switch means is in said first position, from said office. | | | This is accomplished by a programmed controller operating a switch which disconnects the DAA connected to the central station and connects a current generator to operate the data processing circuit of the station. | | | The modem of claim 1 wherein wherein said data processor is adapted to communicate with at least one of a speaker, a microphone. |
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http://www.freepatentsonline.com/6272210.html
(2010 words)
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| | Symmetric multiprocessing: Definition and Much More From Answers.com |
| | SMP systems allow any processor to work on any task no matter where the data for that task is located in memory; with proper operating system support, SMP systems can easily move tasks between processors to balance the work load efficiently. | | | SMP has many uses in science, industry, and business where software is usually custom programmed for multithreaded processing. | | | Symmetric Multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors are connected to a single shared main memory. |
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http://www.answers.com/topic/symmetric-multiprocessing
(1197 words)
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| | EMC CLARiiON, StorageTek, Backup, Users: Data General |
| | Supports both Programmed and Data Channel I/O. Hawk-E. (P/N 9322 E) Basic Hawk Co-Processor card set with 2.0 Mbyte memory and microcoded instructions for Nova 4X and Eclipse S280. | | | Replaces Data General 1.2 Mbyte floppy drive (Part No. 6097). | | | Create your Data General disk images as container files on PC – host disk(s). |
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http://www.bltrading.com/nova.htm
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| | EMC CLARiiON, StorageTek, Backup, Users: Data General |
| | Supports both Programmed and Data Channel I/O. Hawk-E. (P/N 9322 E) Basic Hawk Co-Processor card set with 2.0 Mbyte memory and microcoded instructions for Nova 4X and Eclipse S280. | | | This is all it takes to execute your Nova or Eclipse application on a PC with the Hawk Co-Processor. | | | Replaces Data General 1.2 Mbyte floppy drive (Part No. 6097). |
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http://www.bltrading.com/nova.htm
(1114 words)
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| | Running Programs in Parallel |
| | rather than take data to the processors it is possible to take the processors to the data, by implementing a large number of very simple processors in association with columns of bits in memory | | | thus groups of processors can be programmed to work together, manipulating all the bits of stored words. | | | or might be co-processors which attach to general purpose processors |
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http://www.ee.surrey.ac.uk/Personal/R.Webb/l3a15/tsld187.htm
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| | Work Breakdown Structure (WBS) |
| | The automatic data process equipment element refers to a machine or group of interconnected machines consisting of input, storage, computing, control, and output devices which use electronic circuitry in the main computing element of automatically perform arithmetic and/or logical operations by means of internally stored or externally controlled programmed instructions. | | | This element includes; for example, a central processor, large-capacity storage data channels, input/output, and that peripheral equipment in operational support of data processing equipment, and devices that are designed to convey data form its original state to a data-processing media. | | | The prime mission equipment element refers to the equipments and associated computer programs used to accomplish the prime mission of the defense materiel item. |
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http://www.nnh.com/ev/wbs.html
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| | 23079.980528&ELEMENT_SET=DECL |
| | For example, if the telecommunication system 102 uses a dual tone multi-frequency signal (DTMF, hereinafter "a tone") as a call trigger, the interworking unit 114 can be programmed through software in the digital signal processor to detect the tone during user communications processing. | | | The telecommunication system of claim 1 wherein the interworking unit is configured to process call trigger data and to transmit call trigger data to the signaling processor when the call trigger data is within a subset of call trigger data. | | | If the signaling processor 112 determines that the call trigger is valid, the signaling processor may transmit a processor control message to the interworking unit 114 instructing the interworking unit to route the user communications to the third communication device 110 over a selected connection 128. |
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http://www.wipo.int/cgi-pct/guest/getbykey5?KEY=98/23079.980528&ELEMENT_SET=DECL
(12873 words)
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| | Power supply and power monitor for electric meter - Patent 4591782 |
| | An electronic processor such as, for example, a microprocessor may be employed to manage the acquisition, storage, processing and display of the usage and demand data. | | | This initiates the writing of data from the volatile random access memory in processor 52 to non-volatile memory 64. | | | In order to provide safe storage for data and/or programmed constants during a power outage, a conventional non-volatile memory 64 is provided into which such data and constants can be written in the event of a power outage and from which the data and constants can be again read upon restoration of normal conditions. |
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http://www.freepatentsonline.com/4591782.html
(4400 words)
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| | Data processor system capable of providing both a computer mode and a sequencer mode of operation - Patent 4344129 |
| | A data processor system is capable of operating in a first mode comprising a computer mode so as to carry out data processing functions and is also capable of operating in a second mode comprising a sequencer mode so as to carry out high speed sequence operations on the basis of programmed sequences. | | | A high speed change between the computer and sequencer modes can freely be effected by executing mode change instructions so that the data processor system performs the duplex functions of a computer and a sequencer. | | | During the computer mode of operation, processing not achieved by the above-mentioned sequence instruction is carried out, this processing including analog to digital conversion of analog information fetched by the analog input unit, arithmetic data operation, and the like. |
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http://www.freepatentsonline.com/4344129.html
(5871 words)
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| | Eureka Technology - DDR2 SDRAM Controller IP core |
| | The SDRAM Controller data path then re-synchronize the data and transfers them using the double data rate. | | | ODT support is optimized for single or multiple termination of the data path. | | | They can also be reprogrammed during run time if the user wishes to change them to optimize system performance. |
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http://www.eurekatech.com/products/memory/ep532.htm
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| | DMA reverts to PIO |
| | The alternative, slow and inefficient data transfer mode is called PIO, Programmed Input-Output, where the central processor transfers data byte for byte or word for word. | | | This requires many processor commands for each data word and therefore causes a high and unwanted processor load. | | | You can use the procedure described below, but your computer will probably fall back to PIO mode again and again, until you solve the underlying problem, which may be located inside the device, on the motherboard, or in the IDE data cable and its connectors. |
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http://www.michna.com/kb/WxDMA.htm
(818 words)
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| | Use of other processors during BIOS boot sequence to minimize boot time - US Patent 6336185 |
| | A personal computer system as defined in claim 20, wherein said processors are programmed to complete execution of any boot sequence task, after the initiation of the boot sequence task, without reference to data or the execution of any other processor. | | | This is accomplished by creating a parallel boot sequence path for at least one other processor in addition to a boot strap processor, such that this other processor executes certain boot sequence functions that enhance the boot sequence flow, but does not interfere with the boot strap processor (BSP) operation. | | | causing said first peripheral processor to execute a task in said plurality of boot sequence tasks that is different from the task being executed by said boot strap processor and is executed at least partially in parallel with the execution of the at least one task by said boot strap processor. |
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http://www.patentstorm.us/patents/6336185.html
(3680 words)
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| | United States Patent: 5,559,798 |
| | For a given service rate r.sub.i video pre-processor 218 is programmed to minimize costs employing a Viterbi-like process subject to the constraint of source buffer 206 having a size B, and b.sub.i is the amount of compressed video data that actually resides in source buffer during the transmission of interval i video. | | | The aforementioned problems are solved, in accordance with the principles of the invention, by providing for the :segmentation of data exhibiting an intrinsic long-term average data rate, punctuated with 5periods of peak rate data bursts. | | | Such a system is responsive to the rate at which new calls or requests for connections enter and leave the network, the frequency and duration of extended peak rate data bursts, as well as the occurrence of short duration data transmission peaks. |
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http://www.eecs.berkeley.edu/~dtse/rcbr2_patent.html
(3770 words)
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| | Embedded Pentium® Processor Family Technical Information Center - Floating-Point Unit |
| | Note that the FPU's word-integer data type is identical to the word-integer data type used by the processor's integer unit and the short-integer format is identical to the integer unit's doubleword-integer data type. | | | A pointer to the FPU data register that is currently at the top of the FPU register stack is contained in bits 11 through 13 of the FPU status word. | | | Like the general-purpose registers in the processor's integer unit, the contents of the FPU data registers are unaffected by procedure calls, or in other words, the values are maintained across procedure boundaries. |
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http://www.engr.udayton.edu/faculty/jloomis/ece314/notes/fpu/fpu.html
(7054 words)
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| | TcIA_overview.txt |
| | The TURBOchannel interface ASIC in Programmed I/O Programmed I/O transactions (PIO) occur in response to a system processor's load/store instructions to the option's slot in the physical address space. | | | The byte mask allows selecting any of the four bytes comprised in the 32-bit TURBOchannel data word; a bit-value of 0 in the byte mask enables the corresponding byte of the data word. | | | In case a DMA transaction is interrupted because of an error, the current value in the TDP or RDP serves to locate the error exactly in the data stream. |
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http://ftp.digital.com/pub/DEC/TriAdd/TcIA_overview.txt
(4761 words)
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| | Vas's M.Phil Chapter 2 Operational Models of Parallel Computers |
| | Systolic arrays can be programmed to allow data to flow in several dimensions and several directions around the grid. | | | Systolic arrays, however, use that data item to perform a calculation at every processor in the chain before returning a it back to main-memory, see figure 2.4-1. | | | Systolic arrays are used in compute bound applications with data locality. |
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http://www.gigaflop.demon.co.uk/comp/chapt2.htm
(4761 words)
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| | * PDP - (Computing): Definition |
| | The original aim was to make the first small computers for engineering and departmental use, and the PDP (Programmed Data Processor) range became known as minicomputers to contrast them with giant mainframes... | | | PDP-11 (Programmed Data Processor-11) is one of the most famous computers in computing history, one of a series manufactured by Digital Equipment Corporation () from the early 1960s through the mid-1990s... | | | IP is an example of a PDP supported by GPRS... |
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http://en.mimi.hu/computing/pdp.html
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| | ipedia.com: PDP-10 Article |
| | The PDP-10 was a computer manufactured by Digital Equipment Corporation from the late 1960s on; the name stands for "Programmed Data Processor model 10". | | | The PDP-10 was a computer manufactured by Digital Equipment Corporation (DEC) from the late 1960s on; the name stands for "Programmed Data Processor model 10". | | | It was the machine that made time-sharing common; it looms large in hacker folklore because of its adoption in the mid-1970s by many university computing facilities and research labs, including MIT 's AI Lab and Project MAC, Stanford 's SAIL, and CMU. |
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http://www.ipedia.com/pdp_10.html
(4761 words)
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| | papers : paper 2002/3 |
| | The connection is based on networking software programmed in the processor device and a gateway server, which together transfer data between the PSTN and other communication networks. | | | Besides the low cost, the proposed system has several benefits, such as uncomplicated structure and operation, standardized data transfer, and an ability to be embedded in an 8-bit processor device. | | | The data communication utilizes the Short Message Service (SMS) and the Extended Machine Interface (EMI) protocol. |
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http://www.itcon.org/cgi-bin/works/Show?2002_3
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| | index.asp?layout=articlePrint&articleID=CA430897 |
| | Recent processor product designs allow unique die identifiers to be programmed at wafer sort based on a combination of lot number, wafer scribe and X-Y probe location. | | | As models are improved that relate wafer sort parametrics with final device performance, this will eventually lead to trusted models for similar relationships between fab metrology data, e-test, wafer sort and final test. | | | AMD Opteron processor yield trend vs. wafer count was steeper than that for prior processor introductions, despite its being a new product on a new 130 nm process. |
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http://www.reed-electronics.com/SEMICONDUCTOR/index.asp?layout=articlePrint&articleID=CA430897
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| | KIM-I Hardware Manual V1.0 |
| | The 8 lines of the Peripheral A I/O port therefore contain either input or output data depending on whether the line is programmed to act as an input or an output. | | | Each set of 8 input or output lines (referred to as "PORT") is given an address and the processor simply writes data to that address. | | | Thus, an eight-bit data bus is a set of 8 lines which can be assigned a value of logic 0 or logic 1. |
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http://www.kim-1.com/hwman.html
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| | Message formatting, authentication, and error detection in home control systems - US Patent 6690289 |
| | An electrical component as recited in claim 32, wherein the shared key value is from a sequence of key values, the processor being further programmed to change from a current to a subsequent key value in the sequence without notifying a receiving component. | | | An electrical component as recited in claim 39, wherein the shared key value is from a sequence of key values, wherein the processor calculates the sequence of key values using a one-way function of a counter value that advances to generate each sequential key value. | | | The message authentication code for a message within a particular group is derived from message data and from a key value that is shared between the components of the group. |
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http://www.patentstorm.us/patents/6690289.html
(8199 words)
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| | Motorola MC6845 Cathode Ray Tube Controller |
| | Internal CRTC registers are programmed by the processor through the data bus, D0--D7, and the control signals -- /W/R, /CS, RS and E. The nineteen registers of the CRTC may be accessed through the data bus. | | | Vertical registers are programmed in scan line times with respect to the reference as shown in Figure 13. | | | Light Pen (L) The remaining register contents must be determined from some basic data related to the CRT monitor and from the user-desired display format. |
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http://andercheran.aiind.upv.es/~amstrad/docs/mc6845/mc6845.htm
(4325 words)
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| | Embedded Pentium® Processor Family Technical Information Center - Floating-Point Unit |
| | Note that the FPU's word-integer data type is identical to the word-integer data type used by the processor's integer unit and the short-integer format is identical to the integer unit's doubleword-integer data type. | | | A pointer to the FPU data register that is currently at the top of the FPU register stack is contained in bits 11 through 13 of the FPU status word. | | | The first Intel Math Coprocessors (the Intel 8087, Intel 287, and Intel 387) were companion processors to the Intel 8086/8088, Intel 286, and Intel386 processors, respectively, and were designed to improve and extend the numeric processing capability of the Intel Architecture. |
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http://www.engr.udayton.edu/faculty/jloomis/ece314/notes/fpu/fpu.html
(4325 words)
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| | Symmetric multiprocessing - Wikipedia, the free encyclopedia |
| | SMP systems allow any processor to work on any task no matter where the data for that task is located in memory; with proper operating system support, SMP systems can easily move tasks between processors to balance the work load efficiently. | | | SMP has many uses in science, industry, and business where software is usually custom programmed for multithreaded processing. | | | The largest of the large SMP systems is the Cray Research X1, which can be configured off the shelf with as many as 4096 processor packages with four custom designed processor cores per SMP node and a maximum of 32 TiB of memory leading to 52.4 TFLOPS of performance. |
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http://en.wikipedia.org/wiki/Symmetric_multiprocessing
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| | Programmed Input/Output - a Whatis.com definition - see also: PIO |
| | Programmed Input/Output (PIO) is a way of moving data between device s in a computer in which all data must pass through the processor. | | | The Advanced Technology Attachment / Integrated Drive Electronics standard specifies three PIO data transfer rates (mode 0 at 3.3 MBps, mode 1 at 5.2 MBps, and mode 2 at 8.3 MBps). | | | The newer Advanced Technology Attachment standard specifies two higher data transfer rates (mode 3 at 11.1 MBps and mode 4 at 16.6 MBps). |
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http://whatis.techtarget.com/definition/0,,sid9_gci214298,00.html
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