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| | VLIW: old architecture of the new generation |
 | | VLIW processors are an example of the architecture for which the program gives precise data on parallelism - the compiler reveals parallelism in the program and notifies the hardware on which operations do not depend on each other. | | | The main problem of the VLIW processors is evidently a contradiction between the sequential logic of applications and nature of most computational algorithms, and a parallel nature of execution of the VLIW processor. | | | But if in development of an effective VLIW compiler for higher-level languages the developers face such big problems, what can be said about a compiler of such chaotic and unpreductable computer code as the x86, especially considering that it's optimized during compilation for other architectural features. |
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http://www.digit-life.com/articles2/vliw
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| | Very long instruction word - Wikipedia, the free encyclopedia |
| | Prior to VLIW, the notion of prescheduling functional units and instruction level parallelism in software was well established in the practice of developing horizontal microcode. | | | His original development of Trace Scheduling as a compilation technique for VLIW was developed when he was a graduate student at New York University. | | | Multiflow implemented its VLIW in an MSI/LSI/VLSI mix packaged in cabinets, a technology that fell out of favor when it became possible to integrate all of the components of a processor (excluding memory) on a single chip. |
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http://en.wikipedia.org/wiki/VLIW
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| | Simulation/evaluation environment for a VLIW processor architecture |
| | VLIW implementations have been described as "a natural successor to RISC," because complexity is moved from the hardware into the compiler. | | | Since a VLIW processor is characterized by having many functional units, the execution of an instruction pair as two separate instructions might not be detrimental as long as the pair is not in the critical path of the program (neglecting penalties arising from having larger code size). | | | The preparation phase, in which ForestaPC (VLIW) assembly language code [6] is translated into PowerPC assembly code which emulates the behavior of the VLIW program (on a file-by-file basis if the program consists of multiple files). |
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http://www.research.ibm.com/journal/rd/413/moreno.html
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| | VLIW - a Whatis.com definition - see also: very long instruction word |
| | VLIW is sometimes viewed as the next step beyond the reduced instruction set computing (RISC) architecture, which also works with a limited set of relatively basic instructions and can usually execute more than one instruction at a time (a characteristic referred to as superscalar). | | | Very long instruction word (VLIW) describes a computer processing architecture in which a language compiler or pre-processor breaks program instruction down into basic operations that can be performed by the processor in parallel (that is, at the same time). | | | The main advantage of VLIW processors is that complexity is moved from the hardware to the software, which means that the hardware can be smaller, cheaper, and require less power to operate. |
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http://whatis.techtarget.com/definition/0,289893,sid9_gci214395,00.html
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| | VLIW History |
| | VLIW processing ideas have roots in Alan Turing's 1946 parallel computing studies and Maurice Wilkes's 1951 microprogramming work. | | | Once these pioneering companies disappeared, little development appeared to happen on the VLIW front, until engineers found the architecture was ideal for quick computation of complex, repetitive algorithms. | | | In the 1970s, VLIW was nearly un-implementable due to the prohibitively expensive nature of memory at the time. |
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http://www.ecs.umass.edu/ece/koren/architecture/VLIW/1/history.html
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| | ST CHALLENGE 1st EDITION 2000 All you have to do is dream |
| | VLIW stands for Very Long Instruction Word and is a type of computer architecture developed to provide very high performance in microprocessors without using complicated hardware instruction scheduling and dispatch, which is the approach used in most modern microprocessors. | | | The Custom VLIW technology platform will initiate a new paradigm in SoC design by allowing a customized processor architecture, an optimized compiler and other software tools to be generated with a high degree of automation from an analysis of the proposed application. | | | VLIW reverses the trend towards ever more complex architectures by eliminating the hardware required to re-order and schedule instructions while the program is running. |
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http://www.st.com/stonline/press/magazine/challeng/1stedi00/chal09.htm
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| | MacKiDo/Dojo/EPICisRISC |
| | With VLIW if you try to scale it up to read 6 instructions at a time, it is not an even divisor of 4 -- all the old code is designed for groupings of 4. | | | VLIW (Very-Long Instruction-Word) is a form of RISC, where you can "group" RISC instructions into a bigger "word" -- so big it called a Very-Long Instruction Word -- then it executes all the instructions in parallel. | | | EPIC (Explicit Parallel Instruction Computing) is a form of VLIW, and RISC, with a few additions. |
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http://www.mackido.com/Hardware/EPICisRISC.html
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| | Embedded.com - VLIW Architecture Emerges as Embedded Alternative |
| | The hallmark of VLIW is the ability to extract a highly parallel instruction stream from the applications program with which it is supplied, and dole those machine instructions out to the chip's numerous execution units. | | | By definition, the term VLIW refers to a wide-bit-length word into which must be packed-in advance-the different commands, or op-codes, of all the instructions to be executed simultaneously by the VLIW processor on the next clock cycle. | | | VLIW detractors have argued that any compiler agile enough to effectively schedule so many simultaneous instructions will be overly complex and difficult to write. |
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http://www.embedded.com/story/OEG20010222S0039
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| | VLIW Processors and Trace Scheduling |
| | However the major difference is that unlike the VLIW, SMT tries to optimize system throughput, not execution time of a single task. | | | Because of the difficulty in generating code for these architectures it was not considered practical to build VLIW machines. | | | The VLIW approach simplifies the hardware greatly since all the instruction scheduling and register renaming becomes the duty of the compiler. |
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http://www.cs.utah.edu/~mbinu/coursework/686_vliw/old
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| | Extending Static Synchronization Beyond SIMD and VLIW |
| | However, recent developments, such as VLIW (Very Long Instruction Word) computers [Ell85], are not adequately described by classification as SIMD or MIMD. | | | VLIW (Very Long Instruction Word) machines are successful in large part because they preserve this property while providing more flexibility in terms of what kinds of operations can be parallelized. | | | An SBM machine is, in every way, a superset of a VLIW machine. |
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http://dynamo.ecn.purdue.edu/~hankd/CARP/TREE88_25/paper.html
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| | Glossary Search Results |
| | VLIW uses encoded instructions that are even more complex than the instructions used in CISC. | | | VLIW is used in the Hewlett Packard PA-RISC series of microprocessors, and formed the basis of some of the architecture used in Intel's IA-64 processors. | | | While RISC took instruction sets in a simpler direction by making instructions smaller, VLIW moves them in a more complex direction by encoding four or more instructions into a single operation. |
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http://www.geek.com/glossary/glossary_search.cgi?Very
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| | VLIW Difficulties of Implementation |
| | VLIW has been slow to gain market acceptance due in large part to the human programming difficulties involved. | | | Transmeta has addressed this problem with the development of its Code Morphing technology that allows x86 code to be run on its Crusoe chips, but this problem remains a major stumbling block for corporate VLIW implementations. | | | Early VLIW implementations looked only into basic program blocks to obtain ILP, and could not follow complex branches. |
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http://www.ecs.umass.edu/ece/koren/architecture/VLIW/1/difficulties.html
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| | Reservoir Labs® -- Multiflow VLIW |
| | While Multiflow's compiler (software) was particularly advanced, Multiflow failed as a business due to poor choice of hardware implementation technology: the MSI/LSI components were obsoleted as a computer implementation technology the instant that silicon VLSI technology permitted the integration of CPU, floating point processing and cache on the same chip. | | | The prediction that VLIW architecture would become important in single chip computers has come true: most advanced DSP, media processing, and next generation server processors are based on VLIW architecture and compiler principles. | | | In a sense, Multiflow was too far ahead of its time - the only way to build a VLIW with 28 instruction units in 1985 was with MSI/LSI technology, and this was the technology of choice for building mainframes, minicomputers, and minisupercomputers. |
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http://www.reservoir.com/vliw.php
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| | VLIW at IBM Research |
| | The VLIW effort at the IBM T.J. Watson Research Center started in 1986, leading to our first publications [1, 2] describing a new approach to exploit instruction-level parallelism in branch-intensive programs. | | | The continuing development of tools and an environment to simulate/evaluate the potential benefits of VLIW technology. | | | This approach is based on expressing a program as a sequence of tree-instructions, each of which contains a multiway branch and multiple operations, all executable concurrently. |
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http://www.research.ibm.com/vliw
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| | Fujitsu introduces a VLIW based processor |
| | VLIW architecture allows the compiler rather than the processor to be responsible for guaranteeing simultaneous issuing of each packet, as opposed to a superscalar processor which has to decide itself whether or not multiple instructions can be executed at the same time. | | | Packed VLIW instructions can be placed on memory without increasing instruction memory size. | | | The processor core of the FR500 fetches the packed instruction using instruction cache and unpacks it to configure a four 32-bit instruction VLIW. |
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http://www.hoise.com/primeur/00/articles/monthly/AE-PR-03-00-49.html
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| | VLIW |
| | The most famous VLIW machine was built by (the late) Multiflow Computer, Inc. | | | (VLIW) Used to describe an assembly language instruction set implemented using horizontal microcode. | | | They are static in the sense that which units operate in parallel is determined by the instruction rather than by dynamic scheduling at run time. |
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http://www.linuxguruz.com/foldoc/foldoc.php?VLIW
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| | Results for 'VLIW Microprocessors' |
| | Welcome to IEEE Xplore 2.0: Computer Design: VLSI in Computers and Processors, 2002. | | | VLIW with various characteristics have been explored to find an optimal processor implementation for this... | | | VLIW design, supporting sub-word parallelism with an extensive instruction set optimized with... |
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http://odysseus.ieee.org/ieeesearch/query.html?qt=VLIW+Microprocessors
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| | BYTE.com |
| | In a pure VLIW world, moving from one generation of a processor family to another one means that you have to recompile all your code. | | | VLIW provides a natural way to split up the CISC instructions into the basic RISC-like operations that would then be executed by the different logical units of the VLIW machine. | | | VLIW compilers are responsible for determining which instructions depend on others. |
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http://www.byte.com/art/9411/sec12/art1.htm
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| | BYTE.com |
| | In hardware terms a VLIW processor is very simple, consisting of little more than a collection of function units (adders, multipliers, branch units, etc.) connected by a bus, plus some registers and caches. | | | While VLIW ideas have been around since the dawn of computing--Turing designed a VLIW computer in 1946--none has been commercially successful. | | | Behind the renewed interest in VLIW architectures for general-purpose computing lie significant advances in compiler design over the last decade. |
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http://www.byte.com/art/9604/sec8/art3.htm
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| | Citations: Superscalar vs. VLIW - O'Donnell (ResearchIndex) |
| | A program binary compiled for VLIW generation X cannot be guaranteed to execute correctly on generations X n or X Gamma n, for a reasonable value of n. | | | Keywords VLIW, Object Code Compatibility, Dynamic Rescheduling, Instruction Level Parallelism 2 I. Introduction Lack of object code compatibility across generations of a VLIW architecture is an often raised objection to its use as a general purpose computing paradigm | | | This is known as the object code compatibility problem in VLIW architectures [4] Lack of object code compatibility is a commonly cited reason why VLIWs may not become a general purpose computing paradigm |
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http://citeseer.ist.psu.edu/context/1329476/0
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| | Handling Irregular ILP Within Conventional VLIW Schedulers Using Artificial Resource Constraints |
| | The artificial resources are generated by solving a combinatorial graph labeling problem which is generated from the ISA specification. | | | In this paper we show how the irregularities in the ISA can actually be matched with the regular resource based requirements of classic VLIW compilers by generating a set of artificial resources based on the ISA specification. | | | However, the ISAs (Instruction Set Architectures) for these machines are still driven by embedded processing constraints (small code size, simpler hardware), and consequently all available ILP may not always be cleanly reflected in the ISA. |
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http://www.gigascale.org/pubs/89.html
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| | Transmeta Corporation : Crusoe > Architecture > 128-bit VLIW Engine |
| | The VLIW design of the Crusoe processor avoids this power and transistor penalty by implementing such complexities with its Code Morphing software. | | | However, a large fraction of the transistor count in traditional processors is devoted to rearranging instructions for optimal parallel execution. | | | processor enables a new class of low power computing and x86 software compatibility by combining the energy efficiency of a VLIW (very long instruction word) engine with the versatility of the innovative Code Morphing |
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http://www.transmeta.com/crusoe/vliw.html
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| | HP Labs : News : VLIW Pioneer Wins Computer Architecture's Most Prestigious Award |
| | VLIW computing is a CPU architecture that reads a group of instructions and executes them all at the same time. | | | Fisher's pioneering research on VLIW, which enables faster processing, and his work on ILP and custom-fit processors, widely used in special-purpose devices such as mobile phones, have had a lasting impact on much of computer architecture, the technical organizations said. | | | While a member of the computer science faculty at Yale University, he developed many of the basic techniques of compiler-controlled ILP, coining the terms VLIW and ILP in the process. |
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http://www.hpl.hp.com/news/2003/apr_jun/fisher_award.html
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| | Miroslav Velev's SAT Benchmarks |
| | These formulas are from buggy variants of a more complex VLIW processor than the one used for VLIW-SAT-2.0. | | | B5 100 big satisfiable CNF formulas, generated in the formal verification of buggy variants of a VLIW microprocessor. | | | These formulas are from buggy variants of the most complex model in VLIW-UNSAT-4.0. |
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http://www.ece.cmu.edu/~mvelev/sat_benchmarks.html
(785 words)
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| | Very Long Instruction Word Processors (VLIW) |
| | Very long instruction word (VLIW) ideas came from the parallel microcode way back in computing's earliest days and from the first supercomputers such as the Control Data CDC6600 and IBM 360/91. | | | While both those VLIW machines used multiple chips, some regard Intel's i860 as the first single-chip VLIW. | | | In the 1970s, many attached array processors and dedicated signal processors used VLIW-like wide instructions in ROM to compute fast Fourier transforms and other algorithms. |
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http://web.ukonline.co.uk/p.boughton/vliw.htm
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| | Slashdot AMD Releases X86-64 Architecture Programmers Overview |
| | Thus (in theory) the VLIW chip can be a lot simpler, since it doesn't need to spend a whole bunch of chip area on complicated logic to manage the process of choosing which instructions to process simultaneously and on large buffers to hold many instructions while the fastest combinations are chosen. | | | The difference with VLIW is that several instructions are held in the same instruction word. | | | Basically, VLIW design can be (roughly) thought of as focusing on the question "given chip process design circa , and problem space , and assuming very clever compilers, what's the optimal ISA we can implement?" |
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http://www.slashdot.org/articles/00/08/10/1013241.shtml
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| | HP helps put VLIW into STMicro's system-chip |
| | In this sense, the ST210 is a much purer form of VLIW as envisioned by the creators of the instruction set and compiler technology. | | | "At the time, there was a lot of interest in VLIW as a technique to increase processing power for a given size by way of increasing the software tool complexity," said Richard Bramley, R&D manager for STMicroelectronics. | | | While STMicro started investigating VLIW, Hewlett-Packard's R&D division, HP Labs, was working on its own VLIW technology in several forms. |
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http://www.embedded.com/shared/printableArticle.jhtml?articleID=9900461
(907 words)
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| | Citations: MHz VLIW mediaprocessor - O'Donnell (ResearchIndex) |
| | VLIW architectures, first described by Josh Fisher [7] have been common in programmable media processors due to their ability to effectively exploit instruction level parallelism. | | | 1996] and Intel s MMX [Peleg and Weiser, 1996] VLIW architectures [Fisher, 1983] have been common in programmable media processors due to their ability to effectively exploit instruction level parallelism. | | | The field of computer graphics has seen both architectures of varying programmability and architectures which use.... |
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http://citeseer.ist.psu.edu/context/1168662/0
(248 words)
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| | VLIW Microprocessors - Computerworld |
| | But beyond that, VLIW has become the prevailing philosophy of microprocessor design, eclipsing older approaches such as RISC and complex instruction set computing (CISC). | | | VLIW is the latest way to simplify processors. | | | The software development tools that programmers use to compile their programs into executable code are responsible for arranging the instructions in the most efficient manner. |
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http://www.computerworld.com/news/2000/story/0,11280,43018,00.html
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| | Citations: Bulldog: A compiler for VLIW architectures - Ellis (ResearchIndex) |
| | A first approach is to determine the required data routes during the execution of the scheduling algorithm. | | | Using a trace, it is possible to expose available ILP because several basic blocks are included in it, which can be scheduled in parallel on the underlying VLIW processor as a single unit. | | | Using a trace, it is possible to expose available ILP because several basic blocks are included in it which can be scheduled in parallel on the underlying VLIW processor. |
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http://citeseer.ist.psu.edu/context/10699/0
(1376 words)
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| | Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools |
| | This change is bringing in a new age of embedded computing design, in which a high-performance processor is central. | | | Since this book is about embedded computing, we define and explore that world in general, but with the strongest emphasis on the processing aspects. | | | Historically, the embedded computing community has rarely been related to the VLIW community. |
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http://www.vliw.org/book
(374 words)
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| | Fool.com: Inside Intel Again: Merced vs. Crusoe [Rule Maker] February 25, 2000 |
| | The Crusoe translates IA32 instructions to VLIW in software and reorganizes the resulting code to keep all the processor cores busy. | | | Instead, it designed them to use VLIW software. | | | On a four-core VLIW chip, each VLIW instruction consists of four RISC instructions glued together, one after the other. |
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http://www.fool.com/portfolios/rulemaker/2000/rulemaker000225.htm
(1825 words)
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| | EETimes.com - STMicro readies Bluetooth SoC, VLIW cores |
| | But at the same time, the VLIW architecture is weak at interpreting complex "spaghetti" code, Commins said. | | | To stand out, ST is relying on the customizable nature of its VLIW instruction sets, which can be optimized for particular applications, Commins said. | | | In fact, ST said it plans to wield VLIW only for those specific tasks it handles well. |
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http://www.eetimes.com/story/OEG20001214S0023
(880 words)
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| | Compilers - How about VLIW used as RISC? |
| | VLIW is only interesting if you want to build a one way (one instruction | | | > VLIW is only interesting if you want to build a one way (one instruction | | | The final result may be VLIW, where each word contains many RISC type |
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http://www.codecomments.com/archive285-2004-5-185507.html
(1329 words)
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| | Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures |
| | Performance evaluation is described for 11 benchmark programs based on the IBM VLIW research compiler, Chameleon. | | | Ebioglu, and T. Nakatani,, “A new compilation technique for parallelizing loops with unpredictable branches on a VLIW architecture,” Languages and Compilers for Parallel Computing, pp. | | | Very Long Instruction Word (VLIW) architectures can enhance performance by exploiting fine-grained instruction level parallelism. |
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http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/trans/td/&toc=comp/trans/td/2001/12/lztoc.xml&DOI=10.1109/71.970564
(957 words)
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| | Transmeta Corporation : Efficeon > Architecture > 256-bit VLIW Engine |
| | This unique combination of hardware and software allows the processor to be more streamlined and adds intelligence to the Efficeon processor not found in other x86 microprocessors. | | | CMS dynamically optimizes and translates x86 instructions into VLIW native code that the VLIW hardware engine can process. | | | High Performance 8 Instruction Issue, 256-Bit VLIW Engine |
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http://www.transmeta.com/efficeon/vliw.html
(242 words)
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| | DAISY -- Architecture Emulation thru Dynamic Compilation |
| | To attack this compatibility problem, DAISY introduces simple hardware features intended to simplify emulation of existing architectures, so that all existing software for an old architecture (including operating system kernel code) runs without changes. | | | Other issues dealt with in the Report include self-modifying code, precise exceptions, and aggressive reordering of memory references in the presence of strong MP consistency and memory mapped I/O. Initial results are reported from a DAISY implementation mapping PowerPC to a VLIW architecture. | | | A demonstration and tutorial of this algorithm may be viewed online, as can a detailed Research Report, |
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http://www.research.ibm.com/daisy
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| | TINKER LEGO DOC: VLIW class Reference |
| | Referenced by check_bypass(), check_macro_bypass(), init(), output(), print(), process_pipeline(), and VLIW(). | | | Referenced by init(), output(), process_pipeline(), VLIW(), and ~VLIW(). |
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http://www.tinker.ncsu.edu/LEGO/doxygen/html/classVLIW.html
(463 words)
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| | Code-morphing: Fresh as a DAISY Tech News on ZDNet |
| | For its part, Transmeta has said it plans to release an updated version of its code-morphing software in the first quarter of 2001. | | | IBM Research's DAISY also is aimed at providing compatibility between X86 software and IBM's VLIW processors. | | | The DAISY research project focuses less on low power and more on achieving instruction level parallelism in a server environment and on convergence of different architectures on a common microprocessor core. |
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http://news.zdnet.com/2100-9595_22-525936.html?legacy=zdnn
(557 words)
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| | 64-Bit CPUs: What You Need to Know |
| | Broadsiding a processor with a volley of instructions at once is what VLIW is all about. | | | IA-64's groups also reduce the code bloat seen in traditional VLIW designs (where fixed-width VLIW instruction slots may often go unused if the compiler cannot find independent instructions to group together from within a particular window of instructions). | | | Pedantic computer architects may argue over abstruse differences, and Intel's marketing people will steam over the misuse of their trademark, but for all intents and purposes, EPIC is merely a more pronounceable rendition of VLIW with a few enhancements. |
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http://www.extremetech.com/article2/0,3973,1155599,00.asp
(787 words)
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| | mAgic VLIW presented at Stanford conference |
| | MAgic VLIW surface is about 25 square millimetres, equal to a fourth of a little finger nail, and it is able to do a billion and a half operations per second, spending only half a watt, which means fifty times less than a personal computer with the same computing power. | | | The new component has been conceived mainly to create the so-called environment intelligence, generally considered next bound of electronics. | | | Thanks to its very high computing power, mAgic enables to create miniaturized electronic systems able to elaborate in real-time, audio, ultrasonic and radio complex signals in input and output. |
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http://www.eurekalert.org/pub_releases/2003-08/indf-pis080103.php
(746 words)
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| | VLIW at IBM Research |
| | That is, is it possible to write a VLIW program in machine-level language, in such a way that the same program can be used in different implementations of the same architecture? | | | That is, is it possible to exploit VLIW techniques as an extension to existing architectures? | | | If not, how can existing code be executed efficiently on a VLIW architecture? |
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http://www.research.ibm.com/vliw/proj.html
(140 words)
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| | HP sued over very long instruction word (VLIW) technology |
| | VLIW Technology LLC, according to reports, wants HP to stop distributing VLIW (very long instruction word) technology to others after it allegedly licensed the design in 1990. | | | A FIRM IS TAKING legal action against Hewlett Packard over very long instruction word (VLIW) programming in a move which may also have implications for the Intel Itanium processor, which uses elements of VLIW developed by HP. | | | HP used elements of VLIW technology in EPIC, which it described as an evolution of this style of architecture. |
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http://www.theinquirer.net/?article=6734
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| | ElectronicsWeekly.com - IMEC develops VLIW, coarse-grained DSP |
| | The VLIW DSP efficiently executes control-flow code by exploiting instruction-level parallelism, IMEC said. | | | Future research will focus on improving the memory hierarchy, developing the control path and a systematic architectural exploration methodology. | | | This architectural flexibility and C design flow allows a designer to rapidly explore architectural options for an application domain; applications can be programmed completely in C. IMEC currently has a functioning prototype of the retargetable compiler and is conducting ongoing research in benchmarking the architecture in terms of power, performance and area. |
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http://www.electronicsweekly.co.uk/Article5333.htm
(288 words)
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| | VLIW : Java Glossary |
| | The Java JIT solves the code distribution problem neatly, since the common JVM class files can be compiled as the last minute into the required VLIW format. | | | Intel is working on a new type of CPU that uses very long instruction words instead of microcode. | | | You are here : home : Java Glossary : V words : VLIW. |
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http://www.mindprod.com/jgloss/vliw.html
(161 words)
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| | EETimes.com - Transmeta's Ditzel looks to VLIW's future at Micro-31 |
| | Reiterating an insight made by other knowledgeable architects, Ditzel noted that VLIW relies on a balance between hardware and software. | | | Instead, Intel has coined the moniker "Explicitly parallel instruction computing," or Epic. | | | "Largely, VLIW has been a technique waiting for technology to catch up," Ditzel said. |
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http://www.eet.com/story/OEG19981201S0003
(966 words)
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| | vliw* - OneLook Dictionary Search |
| | VLIW : Free On-line Dictionary of Computing [home, info] | | | Tip: Click on the first link on a line below to go directly to a page where "vliw" is defined. | | | We found 10 dictionaries with English definitions that include the word vliw: |
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http://www.onelook.com/?w=vliw*
(128 words)
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| | VLIW - Webopedia.com |
| | Short for Very Long Instruction Word, a microprocessor design technology. | | | A chip with VLIW technology is capable of executing many operations within one clock cycle. | | | Essentially, a compiler reduces program instructions into basic operations that the processor can perform simultaneously. |
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http://itmanagement.webopedia.com/TERM/V/VLIW.html
(73 words)
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| | Compiling to a VLIW Fragment Pipeline |
| | In this paper, we describe in detail the algorithms used by this system to generate and optimize fragment code for NVIDIA's register combiner architecture and show that our compiler generates efficient code. | | | We also discuss some of the lessons we learned from building and using this compiler that may be useful to the designers of future programmable graphics hardware. | | | The register combiner architecture has some similarities to VLIW CPU architectures, so we compare our compilation algorithms to those described in the literature for VLIW CPU architectures. |
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http://www-graphics.stanford.edu/projects/shading/pubs/hwws2001-regcomb
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