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| | Vector processor - Wikipedia, the free encyclopedia |
 | | Vector processors were common in the scientific computing area, where they formed the basis of most supercomputers through the 1980s and into the 1990s, but general increases in performance and processor design saw the near disappearance of the vector processor as a general-purpose CPU. | | | A vector processor, or array processor, is a CPU design that is able to run mathematical operations on multiple data elements simultaneously. | | | The first successful implementation of a vector processor appears to be the CDC STAR-100 and the Texas Instruments Advanced Scientific Computer. |
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http://www.wikipedia.org/wiki/Vector_processor
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| | Vector - Wikipedia, the free encyclopedia |
| | Vector processor, a computer processor which works on arrays of several numbers at once | | | Vector (computing), the method that malicious code (viruses, etc) uses to propagate itself | | | Vector (spatial), an object defined by both magnitude and direction |
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http://en.wikipedia.org/wiki/Vector
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| | Vector processor - Patent 4725973 |
| | A vector processor according to claim 4, wherein said data transfer means includes a first selector connecting said outputs of said vector registers to inputs of said arithmetic logic units, and a second selector connecting outputs of said arithmetic logic units to inputs of said vector registers. | | | The vector processing and the chaining are taught in the literature of Richard M. Russel "The Cray-1 Computer System" in "Communications of the ACM" 1978, Jan. Vol. | | | As explained above, the succeeding vector instruction must be set in a wait state before it reads the operation result of the preceding instruction or the VR for storing the fetched data as its operand. |
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http://www.freepatentsonline.com/4725973.html
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| | OpenVMS System Manager's Manual |
| | All processors in a multiprocessing environment must be at the same hardware and firmware level to guarantee that a given processor is capable of resuming the execution thread of a process that had been executing previously on another processor in the system. | | | Vector computers, on the other hand, recognize vectors as native data structures and can operate on an entire vector with a single vector instruction. | | | Pipelined functional units allow the vector processor to overlap the execution of successive computations with previous computations. |
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http://www.cuis.edu/doc_vms_html/000000/731final/6017/6017pro_108.html
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| | 3.5.1 Vector Processors |
| | In the register to register machines the vectors have a relatively short length, 64 in the case of the Cray family, but the startup time is far less than on the memory to memory machines. | | | .'' In a scalar machine the operands are numbers, but in vector processors the operands are vectors and the instruction directs the machine to compute the pairwise sum of each pair of vector elements. | | | A key division of vector processors arises from the way the instructions access their operands. |
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http://csep1.phy.ornl.gov/ca/node24.html
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| | Method and system for dynamically reconfiguring a register file in a vector processor - Patent 5513366 |
| | This vector instruction may be equivalent to an entire DO loop, in which each iteration of the DO loop includes a computation of one of the 64 elements of the result, an update of the indices, and a branch back to the beginning of the DO loop. | | | Another advantage of using an SIMD-parallel processor is that the computation of each result, or element in a vector, is independent of the computation of a previous result. | | | When recalling a vector from main memory, the high latency of initiating a main memory access (compared with the latency of accessing a cache memory) may be amortized over the access for an entire vector rather than a single element. |
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http://www.freepatentsonline.com/5513366.html
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| | VAX MACRO and Instruction Set Reference Manual |
| | The vector processor state for possible encodings is shown in Table 10-3. | | | VLR is loaded prior to executing the vector instruction using a Move to Vector Processor (MTVP) instruction. | | | When it is clear, the vector processor is idle, or the vector processor has suspended instruction execution due to an asynchronous memory management exception or hardware error. |
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http://www.myths.com/pub/doc/openvms/721final/4515/4515pro_030.html
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| | VAX MACRO and Instruction Set Reference Manual |
| | Vector operate instructions are always executed to completion, even if a vector arithmetic exception occurs. | | | As a result of error conditions or software control, the vector processor signals the scalar processor not to issue any more vector instructions. | | | Ensure the new state of the vector processor becomes visible to the scalar processor by reading VPSR with the MFPR instruction. |
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http://www.cuis.edu/doc_vms_html/000000/731final/4515/4515pro_033.html
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| | Minisupercomputer - Encyclopedia.WorldSearch |
| | As scientific computing in the form of vector processors became more popular, the need for lower-cost systems that might be used at the departmental level instead of the corporate level created a market opportunity for new computer vendors to enter the market. | | | These computer systems were characterized by the combination of vector processing and small-scale multiprocessing. | | | Minisupercomputers* constituted a class of computers that emerged in the mid-1980s. |
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http://encyclopedia.worldsearch.com/minisupercomputer.htm
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| | Vector processor - Patent 5001626 |
| | Vector processors having such a structure have been described in pages 195 to 209 of the Nikkei Electronics, Dec. 16, 1985, and in pages 237 to 272 of the Nikkei Electronics, Nov. 19, 1984. | | | For example, for pipeline arithmetic unit 3 there are disposed an even-numbered element input bus 107-0, and odd-numbered element input bus 107-1, and even-numbered element output bus 108-0, and an odd-numbered output bus 108-1. | | | The result of an OR operation performed on the outputs from the respective selectors 118 and 119 is fed to a write data bus 104. |
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http://www.freepatentsonline.com/5001626.html
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| | [No title] |
| | Each of the processing elements is connected to an input vector data bus via the multiplexer and directly to an I/O data bus, so that two types of input vector data are inputted to the processing element simultaneously. | | | Flags indicating a position of respective vector data are added to each one of input vector data, series composed of a combination of plural types of input vector data series. | | | The Scientific Processor is under task assignment control of the host processor and shares the same memory space as the host processor, and thereby provides the tight coupling without need of dedicated memory or caching. |
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http://lpf.ai.mit.edu/Patents/abstracts/395800.1990-1992
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| | SIMD |
| | It is a computing term that refers to a set of operations for efficiently handling large quantities of data in parallel, as in a vector processor or array processor. | | | The first use of SIMD instructions was in vector supercomputers and was especially popularized by Cray in the 1970s. | | | The main difference between SIMD and DSP is that DSPs were complete processors with their own (often difficult to use) instruction set, whereas SIMD designs rely on the general-purpose portions of the CPU to handle the program details, and the SIMD instructions handle the data manipulation only. |
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http://www.brainyencyclopedia.com/encyclopedia/s/si/simd.html
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| | Vector Processor Caches |
| | Caches have been used mainly for instructions, while data references are usually uncached, presumably partially because of the belief that there is insufficient data locality in vector workloads. | | | In this study we use memory address traces from Cray X-MP and Ardent Titan machines to examine both reference locality and cache performance in a vector processing environment. | | | For further information concerning use of UC Berkeley documents for other than research or instructional purposes, contact the Computer Science Division at the University of California at Berkeley, tr-cs@cs.berkeley.edu. |
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http://sunsite.berkeley.edu/TechRepPages/CSD-92-707
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| | The Performance Impact of Vector Processor Caches |
| | Cache memories have not been used for vector supercomputers, as far as we know, because of a belief that program behavior in relevant workloads was such as to preclude efficient cache operation. | | | In related research, we have found that hit ratios are high for large caches in processors with vector workloads. | | | In this paper, we address the specific issue of the direct effect of cache memory on vector processor performance. |
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http://sunsite.berkeley.edu/TechRepPages/CSD-91-609
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| | Electrosonic VECTOR large screen image processor |
| | VECTOR accepts composite, component and digital video sources, both analog and digital. | | | This makes VECTOR particularly suitable for presentation or simulation oriented displays, that contain high levels of motion in the sources. | | | This real time scaler allows the size and position of sources to be changed on every frame of video, without interruption to the display. |
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http://www.electrosonic.com/vector.shtm
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| | Encyclopedia: PowerPC |
| | PowerPC processors are used in Apple Macintosh, IBM RS/6000 computer, Amiga acceleration boards, the Nintendo GameCube, and many embedded systems such as TiVo. | | | Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors as well. | | | An interesting side-effect of this implementation is that a program can store a 64-bit value (the longest operand format) to an address A while in one endian mode, switch modes, and when the value is read back from A it will be identical, even though ostensibly the processor is now in the opposite byte-order mode. |
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http://www.nationmaster.com/encyclopedia/PowerPC
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| | Bitboys Introduces Vector Graphics Processor for Mobile Devices at Game Developers Conference |
| | Bitboys graphics processors are specifically designed for power and size restricted environments and are the outcome of over 14 years of experience in graphics research and development. | | | Vector graphics allow content to be always rendered to the highest possible detail and quality, while animation is easily executed and takes very little memory. | | | The Bitboys G12 is an extremely compact vector graphics processor that supports hardware rendering of both SVG Tiny 1.2 and OpenVG 1.0 graphics. |
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http://www.us.design-reuse.com/news/news9839.html
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| | PACT-97 Article: B. Goossens. A Multithreaded Vector Co-processor |
| | A locking feature is provided to handle both the reductions and the complex recurrences in a vector form. | | | The Tomasulo's algorithm, simplified to keep the issue and termination logics simple in a multithreaded context, dynamically schedules the dependent instructions. | | | The vector co-processor can run up to 8 vector tasks (threads) in parallel. |
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http://www.pact.sscc.ru/conference/pact97/articles/6661277031.html
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| | The effect of adding a scalar D-cache to the Cray-4 vector processor (ResearchIndex) |
| | When compilers can predict memory access patterns, they vectorize computations and thereby hide the processor/memory disparity. | | | @inproceedings{ steven95the, author = "Beaty, Steven J. and Johnson, Gearold R.", title = "{T}he effect of adding a scalar {D}-cache to the {C}ray-4 vector processor", booktitle = "The First International Conference on Algorithms And Architectures for Parallel Processing", year = "1995", url = "citeseer.ist.psu.edu/51093.html" } | | | Indeed, current vector processors have cycle times far faster than the memories they are connected to. |
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http://citeseer.ist.psu.edu/51093.html
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| | The Berkeley IRAM Project |
| | The Berkeley Intelligent RAM (IRAM) project seeks to understand the entire spectrum of issues involved in designing general-purpose computer systems that integrate a processor and DRAM onto a single chip - from circuits, VLSI design and architectures to compilers and operating systems. | | | IRAM should offer several advantages over today's solutions, including considerably reduced latency and dramatically increased bandwidth to main memory, reduced power and energy consumption, and reduced space and weight for embedded, portable, desktop, and parallel computer systems. |
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http://iram.cs.berkeley.edu
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| | Energy Citations Database (ECD) - Energy and Energy-Related Bibliographic Citations |
| | Availability information may be found in the Availability, Publisher, Research Organization, Resource Relation and/or Author (affiliation information) fields and/or via the "Full-text Availability" link. | | | Energy Citations Database (ECD) Document #5606639 - Local store for scientific vector processor | | | 990210 -- Supercomputers-- (1987-1989); COMPUTERS-- MEMORY DEVICES;COMPUTERS-- VECTOR PROCESSING; COMPUTER ARCHITECTURE;DATA PROCESSING;DATA TRANSMISSION;MATHEMATICS;PERFORMANCE;SCALARS |
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http://www.osti.gov/energycitations/product.biblio.jsp?osti_id=5606639
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| | Hexapedia - List of computing topics |
| | W -ware -- Web browser -- Western Design Center -- Western Design Center 65C02 -- Western Design Center 65816 -- Whitespace -- wiki -- window manager -- Windows 2000 -- Windows 95 -- Windows Me -- Windows NT -- Windows XP -- Word processor -- World wide web -- WYSIWYG -- | | | V Var'aq -- VAX -- VBScript -- Vector processor -- Ventura Publisher -- Very-large-scale integration -- Video editing -- Virtual Memory System -- Virtual memory -- Visual Basic -- Visual FoxPro -- Von Neumann machine -- |
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http://www.hexafind.com/encyclopedia/List_of_computing_topics
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| | Electrosonic VECTOR image processor display types |
| | Outputs may also be overlapped allowing them to be soft-edged mechanically or electronically in front projected applications. | | | C-Through control software allowed source windows to be floated between the displays, accounting for their physical size differences and separation. | | | Source images may be scaled up or down: unlike some processors, scaling is done in a single pass to optimize picture quality. |
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http://www.electrosonic.com/vector_display_types.shtm
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| | Guardian Unlimited Technology Technology Talk of the town |
| | Sony is using cutting-edge CPU technology with its Cell vector processor. | | | The Xbox 360 looks like packing a serious punch, with powerful processors, snappier design and - to the delight of any gaming widows/ers - a lack of wires. | | | I think the PS3 will have the edge for horsepower, and Sony can land the best games. |
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http://www.guardian.co.uk/online/story/0,3605,1486606,00.html
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| | Is vector processor dead? |
| | Is vector processor dead? Ratio of Vector processor to Microprocessor speed vs time |
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http://research.microsoft.com/users/GBell/craytalk/sld086.htm
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| | G4 definition of G4 in computing dictionary - by the Free Online Dictionary, Thesaurus and Encyclopedia. |
| | Introduced in 1999, G4 models were the successor to the G3 series and supported up to 2GB of memory, 64-bit PCI slots and 4x AGP. | | | The G4 CPU included the "Velocity Engine," a vector processor that provides sustained floating point capability up to one gigaflops. | | | Apple's G4 Cube provided a lot of horsepower in an ultra slick and totally quiet unit, but generated excessive heat. |
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http://computing-dictionary.thefreedictionary.com/G4
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| | US PATENT SUBCLASS 712 / 7-- .~.~ Vector processor operation |
| | US PATENT SUBCLASS 712 / 7--.~.~ Vector processor operation | | | (under subclass 2) Subject matter wherein functioning of the vector processor is specified. | | | ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: PROCESSING ARCHITECTURES AND INSTURCTION PROCESSING (E.G., PROCESSORS) |
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http://www.patentec.com/data/class/defs/712/7.html
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